B. De Muer

A 2 V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

A CMOS monolithic /spl Delta//spl Sigma/-controlled fractional-N frequency synthesizer for DCS-1800

A monolithic 1.8-GHz /spl Delta//spl Sigma/-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-/spl mu/m CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2/spl times/2 mm/sup 2/. To investigate the influence of the /spl Delta//spl Sigma/ modulator on the synthesizers spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in /spl Delta//spl Sigma/ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints.

A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO

A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.

The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator

This paper presents the design trade-offs to implement an integrated CMOS quadrature oscillator based on a differential VCO and a differential-to-quadrature converting poly-phase filter. Both the traditional structure, with cascaded building blocks and the appropriate inter circuit buffers, and the merged version, without buffering, are discussed. In the latest, the excessive power consumption in the intermediate buffers is avoided. It is explained how the effect of the poly-phase filter on the phase noise performance of the VCO, can be taken into account in the design, resulting in an optimal trade-off between the overall power consumption and the phase-noise of the quadrature oscillation generator.

A simulator-optimizer for the design of very low phase noise CMOS LC-oscillators

A simulator-optimizer program for spiral inductors on silicon substrates is presented. The program implements the three-dimensional inductance extraction program FastHenry in a simulated annealing optimization loop. The simulated annealing algorithm performs the optimization of automatically generated spiral inductor geometries towards an optimal quality factor for a specified technology. Using the program, a low-phase-noise LC-tank Voltage Controlled Oscillator (VCO) is integrated in a 0.65 /spl mu/m BiCMOS process. The phase noise is as low as -127.5 dBc/Hz at an offset frequency of 600 kHz from a 1.33 GHz carrier, while consuming only 10 mA from a 2 V power supply.

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 μm CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm2.

A single-ended 1.5 GHz 8/9 dual-modulus prescaler in 0.7µm CMOS with low phase noise and high input sensitivity

A dual-modulus divide-by-8/9 prescaler fabricated in a standard 0.7µm CMOS technology is presented. A high speed, single-ended divide-by-2 D-flipflop is realized, based on TSPC (True Single Phase Clock) logic. The circuit minimizes phase noise and exhibits an excellent input sensitivity, without using input buffering nor single-ended to differential conversion. The measured maximum input frequency of the prescaler is 1.5 GHz at a 5V power supply, while consuming 11mA. The minimum required input level is smaller than 110mVrmsover the whole operating range. Measured phase noise is as low as -112 dBc/Hz at 1 kHz and -163 dBc/Hz at large offset frequencies.