Johan Janssens

A 2 V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

A 0.8-dB NF ESD-Protected 9-mW CMOS LNA operating at 1.23 GHz [for GPS receiver]

The GPS L2 band, centered at 1.2276 GHz, is planned to enhance the capabilities of civil GPS to backup the conventional GPS L1 link. As the L2 receiver is required to detect a low power signal, an LNA with extremely low noise figure is required. In addition, the LNA must exhibit a large gain to suppress noise from the subsequent stages. This ESD-protected CMOS LNA meets these requirements.

A 0.8 dB NF ESD-protected 9 mW CMOS LNA

The GPS L2 band, centered at 1.2276 GHz, is planned to enhance the capabilities of civil GPS to backup the conventional GPS L1 link. As the L2 receiver is required to detect a low power signal, an LNA with extremely low noise figure is required. In addition, the LNA must exhibit a large gain to suppress noise from the subsequent stages. This ESD-protected CMOS LNA meets these requirements.

A 10 mW inductorless, broadband CMOS low noise amplifier for 900 MHz wireless communications

A low-power, broadband LNA has been integrated in a standard 0.5 /spl mu/m CMOS process. The presented CMOS LNA offers a noise figure better than 3.3 dB up to 970 MHz while drawing only 3.4 mA from a 3.0 V supply. The circuit employs a topology without on-chip inductors and does not require any tuning or trimming to achieve the performance. The amplifier provides a gain of 14.8 dB in a 700 MHz wide band and has a gain of 9 dB at 900 MHz. The input IP3 is -4.7 dBm. The reverse isolation is higher than 41 dB, making it fit for insertion in a CMOS low-IF receiver.

RF CMOS Design, Some Untold Pitfalls

Since several years research has been carried out on the design of RF circuits in CMOS technologies. Since then, the usability of CMOS for RF design has been demonstrated by several research groups. However, there are still some fundamental problems and limitations which may not be overlooked. The purpose of this work is to present some of those ‘untold pitfalls’ in the design of RF CMOS circuits for fully integrated transceivers for telecommunication applications.

A Single-Chip CMOS Transceiver Front-End for DCS-1800 Wireless Communications

This work describes the design and realization of a low voltage single-chip wireless transceiver front-end in a standard 0.25 μm CMOS technology. The presented prototype integrates the LNA, down-converters, VCO, quadrature generator, up-converter and pre-amplifier on a single die. A high level of integration is achieved by using a low-IF topology for reception, a direct quadrature up-conversion topology for transmission and an oscillator with on-chip integrated inductor. The final objective of this design is to develop a complete transceiver system for wireless communications at 1.8 GHz that can be built with a minimum of surrounding components: only an antenna, a duplexer, a power amplifier and a baseband signal processing chip. The presented circuit consumes 240 mW from a 2.5 V supply and occupies a die area of 8.6 mm2.

Design of broadband low-noise amplifiers in deep-submicron CMOS technologies

In general it is believed that the implementation of low-noise RF amplifiers in CMOS at a power dissipation competitive with bipolar technologies requires the use of narrow-band techniques. In this paper the design of power-efficient broadband low-noise amplifiers is explored, i.e., without using accurately tuned LC-tanks nor exploiting the ‘overdrive’ capabilities provided by on-chip inductors.

A 0.25 µm CMOS I/Q-channel downconversion mixer with active coil for DCS-1800 applications

An I/Q-channel downconversion mixer for the DCS-1800 system has been integrated in a standard 0.25 µm CMOS process. The structure features an implicit single-ended to balanced conversion of the RF input-signal and permits DCS-1800 operation at very low LO levels. An active coil circuit prevents degradation of the conversion gain caused by low-frequency feedback mechanisms. At an LO of -9 dBm, a conversion gain of 24.8 dB, a noise figure of 21.5 dB and an IIP3 of 21 VdBm is achieved.