M. Borremans

A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter

In this paper, a 10-bit 1-GSample/s current-steering CMOS digital-to-analog (D/A) converter is presented. The measured integral nonlinearity is better than /spl plusmn/0.2 LSB and the measured differential nonlinearity lies between -0.08 and 0.14 LSB proving the 10-bit accuracy. The 1-GSample/s conversion rate has been obtained by an, at transistor level, fully custom-designed thermometer decoder and synchronization circuit. The layout has been carefully optimized. The parasitic interconnect loads have been estimated and have been iterated in the circuit design. A spurious-free dynamic range (SFDR) of more than 61 dB has been measured in the interval from dc to Nyquist. The power consumption equals 110 mW for a near-Nyquist sinusoidal output signal at a 1-GHz clock. The chip has been processed in a standard 0.35-/spl mu/m CMOS technology and has an active area of only 0.35 mm/sup 2/.

A 2 V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

A single-chip CMOS transceiver for DCS-1800 wireless communications

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

Low-voltage low-power CMOS-RF transceiver design

Research over the last ten years has resulted in attempts toward single-chip CMOS RF circuits for Bluetooth, global positioning system, digital enhanced cordless telecommunications and cellular applications. An overview of the use of CMOS for low-cost integration of a high-end cellular RF transceiver front-end is presented. Some fundamental pitfalls and limitations of RF CMOS are discussed. To circumvent these obstacles, the choice of transceiver architecture, circuit topology design, and systematic optimization of the different transceiver blocks is necessary. Moreover, optimization of the transceiver as one single block by minimizing the number of power-hungry interface circuits is emphasized. As examples, a fully integrated cellular transceiver front-end, a low-power extremely low noise-figure low-noise amplifier, and a very efficient power amplifier are demonstrated.

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO

A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.

A 12 bit 200 MHz low glitch CMOS D/A converter

A 12-bit 200 MHz CMOS current steering D/A converter is presented. The measured glitch energy is 0.8 pVs. To obtain this very low glitch energy specification, a new driver circuit using a dynamic latch is proposed. The measured INL is better than +/-0.5 LSB. The D/A converter operates at a 2.7 V power supply, it has a 20 mA full swing output current and a 200 MHz conversion rate. The worst case power consumption is 140 mW at the maximum conversion rate. The chip has been processed in a standard 0.5 /spl mu/m CMOS technology.

A 12 b 500 MSample/s current-steering CMOS D/A converter

This 12b 500MSample/s CMOS current-steering D/A converter has a segmented architecture. The 5MSBs are converted using the unary approach. A fully custom-made thermometer decoder is manually laid out to achieve the 500MSample/s update rate. The 7LSBs are converted using the binary approach, where the digital input bits directly control the switches. To minimize latency problems and to optimize dynamic performance, a dummy decoder is inserted between the inputs and the switch transistors. Using this architecture, a trade-off between good static specifications and moderate power complexity of the DAC is achieved.

A 1.5 V, wide band 3 GHz, CMOS quadrature direct up-converter for multi-mode wireless communications

This paper presents a 1.5 V, full CMOS, quadrature, direct upconversion mixer for multi-mode wireless communications. The chip includes both a wide band polyphase filter, the linear quadrature up-conversion mixers and a single-ended output stage. More than 35 dBc mirror suppression has been measured over the 700 MHz to 3 GHz frequency range, without any additional trimming or tuning. Any distortion or intermodulation component is lower than -32 dBc and the LO feedthrough is below -35 dBc up to 3 GHz. The chip has been realized in standard 0.25 /spl mu/m CMOS technology.

A low power, 10-bit CMOS D/A converter for high speed applications

In this paper, the realization of a fully binary 10-bit current steering CMOS DAC is presented. Both the measured INL and DNL are smaller than 0.2 LSB. Better than 60 dB SFDR is achieved for all output signals up to a 30 MS/s Nyquist frequency. For a 1 MHz signal, the chip achieves better than 60 dB SFDR for all update rates up to 800 MS/s. The presented DAC core occupies 0.23 mm/sup 2/. The digital power consumption is only 1 mW for a 30 MS/s Nyquist operation. Based on a fundamental theoretical INL- and DNL-yield analysis, the presented design explores the limits towards the binary and the low-power edges of the design space.

A CMOS dual-channel, 100-MHz to 1.1-GHz transmitter for cable applications

A dual channel wideband transmitter for cable applications with more than a decade frequency coverage consists of two parallel transmitters that are both fully operational from 100 MHz up to 1.1 GHz, Using a single-ended current-mode output topology, the RF output signals are losslessly combined. The on-chip integrated oscillators have measured 55 MHz-1200 MHz tuning range. The 3/sup rd/-order harmonic of the oscillator signal is filtered by a wideband active buffered polyphase filter. Using this filter, a linear mixer topology and a linear output driver, all distortion components are below -40 dBc. Intermodulation products of the two channels are all below -48 dBc. This guarantees that the parallel channels do not disturb the other channels in the frequency band even without any channel-specific filtering. Each channel delivers the required -16 dBm RF output signal in a 75 /spl Omega/ double terminated load. The measured noise floor is situated at -139.8 dBc/Hz. The chip is in standard 0.5 /spl mu/m CMOS.