Jean-Pierre Eggermont

Fully depleted SOI-CMOS technology for high temperature IC applications

Thin-film fully depleted complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) technology is currentlly considered as the best mature contender for high-temperature analog or mixed-mode IC applications in the 200-400 degrees C temperature range. This is demonstrated by measurement results of the high-temperature performances of several operational transconductance amplifiers (OTA) with increasing architecture complexity. High-temperature design techniques are also proposed and validated by measurements

Potential and modeling of 1-/spl mu/m SOI CMOS operational transconductance amplifiers for applications up to 1 GHz

The potential of 1-/spl mu/m SOI complementary metal-oxide-semiconductor (CMOS) technology for the realization of operational transconductance amplifiers (OTAs) with transition frequencies in the gigahertz range is demonstrated. High-frequency device models, design guidelines and frequency limitations are detailed, as well as layout and technology improvements which can be used to boost the transconductance at high frequency and to reduce the source/drain-to-substrate capacitances. One-stage and folded-cascode OTAs have been realized to validate the design methodology.

Magnetic-field sensor based on a thin-film SOI transistor

This paper presents a magnetic sensor on thin-film SOI-SIMOX that takes advantage of a previous bipolar structure, the VCBM (voltage-controlled bipolar MOS transistor) to improve magnetic response with low power consumption. The buried oxide avoids substrate currents, while keeping a high relative sensitivity, up to 50% T−1, of the sensor. The paper introduces the structure and theoretical operation regions for both electric and magnetic features. Experimental results on two devices validate the previous analysis, presenting the main figures of merit. Finally, the total device efficiency parameter is introduced.

Low Frequency Noise Measurements at Elevated Temperatures on Thin-Film SOI n-MOSFET

We have performed low-frequency 1/f noise measurements on thin-film SOI n-MOSFETs up to 250/spl deg/C using a dedicated set-up. We show the superiority of thin-film fully-depleted (FD) SOI n-MOSFETs versus partially-depleted (PD) devices from a noise perspective over temperature. We observe the constancy of 1/f noise with increasing temperature when the device is FD, and observe a new noise contribution which can affect the integrated input referred noise under certain conditions. A first-order explanation is proposed for this additional noise. Results are then compared to the input noise measured on a single stage OTA.We have performed low-frequency 1/f noise measurements on thin-film SOI n-MOSFETs up to 250/spl deg/C using a dedicated set-up. We show the superiority of thin-film fully-depleted (FD) SOI n-MOSFETs versus partially-depleted (PD) devices from a noise perspective over temperature. We observe the constancy of 1/f noise with increasing temperature when the device is FD, and observe a new noise contribution which can affect the integrated input referred noise under certain conditions. A first-order explanation is proposed for this additional noise. Results are then compared to the input noise measured on a single stage OTA.