B. Kazemi Esfeh

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance g m , the output conductance g d , the intrinsic gain A v and the cut-off frequencies f t and f max . Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, g m -A v analogue metrics is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that f t reaches ∼270 GHz in the shortest devices.

28 nm FD SOI Technology Platform RF FoM

This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD SOI) ultra-thin body and buried oxide (BOX) (UTBB) MOSFETs for high frequency applications. RF figures of merit (FoM), i.e. the current gain cut-off frequency (fT) and the maximum oscillation frequency (fmax), are presented for different transistor geometries. The parasitic gate and source/drain series resistances, as well as capacitances and their effect on RF performance are analyzed.

Comparative study of parasitic elements on RF FoM in 28 nm FD SOI and bulk technologies

This work presents a comparison of parasitic elements (capacitances and resistances) in a view of their effect on RF Figures of Merit (FoM) in 28 nm fully-depleted silicon-on-insulator (FD SOI) ultra-thin body and buried oxide (UTBB) MOSFETs and their Bulk counterparts. Complete set of small-signal equivalent circuit elements (both “intrinsic”, i.e. device related and “extrinsic”, i.e. parasitic) are extracted from S-parameters measurements in a frequency range up to 40 GHz. It is shown that detrimental/harmful effect of parasitics, particularly capacitances, is stronger in 28 nm bulk technology compared to 28 FD SOI.

Threshold voltage extraction techniques and temperature effect in context of global variability in UTBB mosfets

Assessment of global threshold voltage (Vth) variability in advanced silicon-on-insulator devices implies careful selection of a Vth extraction technique as different methods are sensitive to different parameters and effects. Our main focus is on experimental assessment of most widely used techniques, such as constant current, transconductance derivative and recently introduced gm/Id techniques. Some comparison with linear extrapolation methods is also provided. It is shown that gm/Id method, using data near threshold, is less sensitive to cross-impact of short channel effects (i.e. subthreshold slope and drain induced barrier lowering) variability. Therefore this method is preferred for extraction of intrinsic Vth variability without parasitic effects. Temperature evolution of global inter-die parameter variability is assessed for the first time. Possible reasons of slight variability temperature dependence are discussed.

Comparative study of non-linearities in 28 nm node FDSOI and Bulk MOSFETs

This work investigates, for the first time to our best knowledge, non-linearities in Fully-depleted Silicon-on-Insulator (FDSOI) MOSFETs and compares them with bulk counterparts. 1^st, 2^nd and 3^rd order derivatives of current-voltage I–V characteristics, followed by Harmonic Distortions of 2^nd and 3^rd order (HD<inf>2</inf> and HD<inf>3</inf>) were extracted based on DC measurements and simulations. Design window (i.e. bias and current conditions) with strongly reduced non-linearity in FDSOI device with respect to the bulk counterpart was identified and reasons of this reduction are discussed. Application of the back-gate bias in FDSOI MOSFET was shown to allow for further improvement of non-linearity.

Back-gate bias effect on FDSOI MOSFET RF Figures of Merits and parasitic elements

This work demonstrates that the back-gate terminal of a 28nm FDSOI MOSFET can be used up to several tens of GHz for signal processing. Furthermore, the dependence of the main RF figures-of-merit on the back gate bias are experimentally extracted using a 3-port characterization in the frequency range of 10 MHz – 26.5 GHz. We propose a small-signal equivalent circuit constructed based on 3-port measurements allowing for more complete extraction of parasitic elements comparing to the 2-ports one. The effect of back-gate bias on cut-off frequencies is demonstrated and explained in terms of its influence on the relevant parasitic elements.

Variability of UTBB MOSFET Analog Figures of Merit in Wide Frequency Range

Inter-die variability of analog figures of merit of ultra-thin body and buried oxide (UTBB) FDSOI MOSFETs was studied in a wide frequency range. We demonstrate that variability in the entire frequency range is small and does not exceed 5%, which is considerably less than in previously published results on SOI FinFETs. An effect of frequency on the analog figures of merit variability is discussed and preliminary explanation is proposed.

Global variability of UTBB MOSFET in subthreshold

Global variability of UTBB MOSFETs in subthresh-old and off regimes is analyzed. Variability of the off-state drain current, subthreshold slope, DIBL, gate leakage current, threshold voltage and their correlations are considered. It is demonstrated that subthreshold drain current variability is not only dependent on the threshold voltage variability, but the effective body factor (incorporating short-channel effects) must also be taken into account.

Back-gate bias effect on UTBB-FDSOI non-linearity performance

This work investigates experimentally the non-linearities of FDSOI MOSFETs from DC to RF frequencies. The effect of the back-gate bias on non-linearity of the device is studied by means of 2nd and 3rd harmonic distortions (HD2 and HD3) extracted from dc I-V curves as well as from large-signal RF measurements using 1-dB and IP3 points. It is shown that the non-linearity is reduced by applying a positive back-gate bias. The reasons for this reduction are increasing of “effective body factor” and lesser mobility degradation with increase of the positive back-gate bias.