E. Heller

Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II–VI Barrier Layers

This paper describes fabrication and modeling of quantum dot channel (QDC) field-effect transistors (FETs). A QDC-FET comprises an array of thin-barrier (~1xa0nm) cladded Si, Ge, or other quantum dots (3xa0nm to 4xa0nm) forming an n-channel on a p-Si layer/substrate between the source and drain regions. Experimental characteristics of fabricated QDC-FETs, consisting of two layers of cladded quantum dot arrays (e.g., SiOx-cladded Si dots and GeOx-cladded Ge dots) serving as the transport channel, are presented. Unlike conventional FETs, QDC-FET structures exhibit step-like ID–VG characteristics and discretely bunched ID–VD characteristics as a function of gate voltage. The transfer characteristics appear to be similar to those of single-electron transistors (SETs). However, QDC-FETs employ transport of many electrons and operate at room temperature. A one-dimensional Tsu–Esaki equation is used to simulate the quantum dot channel and explain the steps in the current–voltage behavior. In particular, the effect of the II–VI barrier layers on Ge dots is modeled. The QDC-FET channel is also modeled as having superlattice-like mini-energy bands whose bandwidth and separation are determined by the dot size, cladding thickness, and barrier height. For a given gate voltage (which determines the carrier concentration), carriers in the inversion channel are transported via mini-energy bands that line up with the Fermi level as the drain voltage VDS is changed, producing step-like multistate electrical characteristics. Formation of the quantum dot channel enables higher-mobility transport on very low-mobility substrates or thin films such as poly-Si. The channel mobility can be further enhanced by partially removing the oxide barrier layer and replacing it with lattice-matched II–VI gate insulator layers.

SPATIAL WAVEFUNCTION-SWITCHED (SWS)-FET: A NOVEL DEVICE TO PROCESS MULTIPLE BITS SIMULTANEOUSLY WITH SUB-PICOSECOND DELAYS

Spatial Wavefunction-Switched (SWS) Field-Effect Transistors (FETs) consist of inversion layers comprising two or more coupled quantum wells (QWs). Carriers can be localized in any of the wells and vertically transferred between them by changing the gate voltage. In addition, carriers can also be laterally transferred between adjacent SWSFET devices by the manipulation of the gate voltages (Vg). This enables processing of two more bits simultaneously by changing the spatial location of the carrier ensemble wavefunction, which in turn determines the state of the device [e.g., electrons in well W2 (01), in W1 (10), in both (11), in neither (00)]. Experimentally, the capacitance-voltage data, having a distinct peak, has been presented in InGaAs-AlInAs two-quantum well structures. The peak(s) are attributed to the appearance of carriers, first in the lower well and subsequently their transfer to the upper well. Use of multiple channels allows for CMOS-like configuration with both transistors having n-channel mobilities. Simulation of an InGaAs SWS inverter computes a gate delay of 0.24ps. A cut-off frequency in excess of 8THz is computed for 12nm channel length InGaAs SWSFETs. Examples, including logic gates and a 3-bit full-adder, are presented to show the reduction of device count when SWS-FETs are employed.

Analysis of In0.52Al0.48As/In0.53Ga0.47As/InP quantum wire MODFETs employing coupled well channels

Abstract A coupled well structure in quantum wire configuration for implementing improved performance ( f T >500 GHz) modulation doped field-effect transistors (MODFETs) is proposed and analyzed. The quantum well transport channel is modified by placing a thin barrier layer adjacent to the standard modulation doped heterointerface, resulting in a coupled quantum well region. Varying the distance between the barrier and the interface provides a means of controlling the location and distribution of the two-dimensional electron gas. Further confinement of the carriers to one-dimension is obtained by methods known in the literature, such as mesa etching and regrowth. It has been found that the peak of the electron distribution for the first confined state, as measured from the modulation doped interface, changes dramatically depending on the location of the thin barrier. In the lattice matched system, In 0.52 Al 0.48 As/In 0.53 Ga 0.47 As/InP, a change in the barrier location of 25 A is accompanied by a shift in the carrier peak of more than 40 A. Implications of this are included in the charge control model, from which the current–voltage ( I d – V d ) and transconductance ( g m – V g ) characteristics are obtained. Additionally, the unity gain frequencies ( f T ) of several variations of this device are calculated.

Indium Gallium Arsenide Quantum Dot Gate Field-Effect Transistor Using II–VI Tunnel Insulators Showing Three-State Behavior

This paper presents an indium gallium arsenide (InGaAs) quantum dot gate field-effect transistor (QDG-FET) that exhibits an intermediate “i” state in addition to the conventional ON and OFF states. The QDG-FET utilized a II–VI gate insulator stack consisting of lattice-matched ZnSe/ZnS/ZnMgS/ZnS/ZnSe for its high-κ and wide-bandgap properties. Germanium oxide (GeOx)-cladded germanium quantum dots were self-assembled over the gate insulator stack, and they allow for the three-state behavior of the device. Electrical characteristics of the fabricated device are also presented.

Design and Analysis of InGaN-GaN Modulation Doped Field-Effect Transistors (MODFETs) for Over 60 GHz Operation

A Modulation-Doped Field-Effect Transistor (MODFET) structure having quantum wire channel realized in InGaN-GaN material system is presented. This paper presents design and analysis of a novel one-dimensional Modulation-Doped Field-Effect transistor (1D MODFET) in InGaN-GaN material system for microwave and millimeter wave applications. An analytical model predicting the transport characteristics of the proposed MODFET device is also presented. Analytical results of the current-voltage and transconductance characteristics are presented. The unity-current gain cutoff frequency (fT) of the proposed device is computed as a function of the gate voltage VG. The results are compared with two-dimensional GaN/AlGaN MODFET and HFET devices. The analytical model also predicts that 0.25 μm channel length devices will extend the use of InGaN-GaN MODFETs to above 90GHz.

Logic Gates Design and Simulation Using Spatial Wavefunction Switched (SWS) FETs

This paper presents the design and modeling of logic gates using two channel spatial wavefunction switched field-effect transistors (SWSFETs) it is also known as a twin-drain MOSFET. In SWSFETs, the channel between source and drain has two or more quantum wells (QWs) layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the two quantum wells layers and it causes the switching of charge carriers from one channel to other channel of the device. The first part of this paper shows the characteristics of n-channel SWSFET model, the second part provides the circuit topology for the SWSFET inverter and universal gates- NAND, AND, NOR,OR, XOR and XOR. The proposed model is based on integration between Berkeley Short-channel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level. The results show that all basic two-input logic gates can be implanted by using n-channel SWSFET only, It covers less area compared with CMOS (Complementary metal–oxide–semiconductor) gates. The NAND-NOR can be performed by three SWSFET, moreover the exclusive-NOR “XNOR” can be done by four SWSFET transistors also AND, OR, XOR gates require two additional SWSFET for inverting.

High Performance (fT~500GHZ) In0.52Al0.48As/In0.53Ga0.47As/InP Quantum Wire MODFETs Employing Asymmetric Coupled-Well Channels

A coupled-well InAlAs/InGaAs quantum wire MODFET structure is proposed, for which simulations predict improved frequency performance (>500 GHz), over a wider range of Vg, as compared to well/wire devices with a standard MODFET heterointerface. A comparison of several transverse potential well profiles, obtained by varying the placement of a thin barrier within a 100 Å finite well, is presented. In all cases, the quantum wires consist of a 0.1 μm long channel and a 150 Å finite-square-well lateral profile. It has been found that the peak of the electron distribution for the first confined state, as measured from the heterointerface, changes dramatically depending on the location of the thin barrier. For quantum wire structures, realized in the lattice matched system of In0.52Al0.48As/In0.53Ga0.47As/InP, a change in the barrier location of 25 Å is accompanied by a shift in the carrier peak of more than 40 Å (~20 Å closer to or farther from the spacer-well interface than in the standard MODFET profile). Implications of this are reflected in the current-voltage characteristics (Id-Vd) and frequency responses (fT-Vg) of the proposed structures.

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain metal oxide semiconductor field effect transistor (MOS-FET). In the SWS-FET, the channel between source and drain has two quantum well layers separated by a high band gap material between them. The gate voltage controls the charge carrier concentration in the quantum well layers and it causes the switching of charge carriers from one channel to other channel of the device. The standard SRAM circuit has six transistors (6T), two p-type MOS-FET and four n-type MOS-FET. By using the SWSFET, the size and the number of transistors are reduced and all of transistors are n-channel SWS-FET. This paper proposes two different models of the SWS-FET SRAM circuits with three transistors (3T) and four transistors (4T) also addresses the stability of the proposed SWS-FET SRAM circuits by using the N-curve analysis. The proposed models are based on integration between Berkeley Shortchannel IGFET Model (BSIM) and Analog Behavioral Model (ABM), the model is suitable to investigate the gates configuration and transient analysis at circuit level.