Babak Matinpour

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10/sup 6/ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit.

A low phase noise X-band MMIC GaAs MESFET VCO

We present a fully monolithic X-band VCO MMIC implemented in a commercial GaAs MESFET process. Measurement results demonstrate a single sideband phase noise of -91 dBc/Hz at a 100 KHz offset. This VCO achieves a maximum output power of 11.5 dBm with 12 dB of output power control and a 550 MHz of frequency tuning range. Second harmonic suppression of 20 dB or more is measured across the entire power and frequency range. These results are comparable to, or better than, the best reported results of VCOs implemented in high electron mobility transistor (HEMT) and heterojunction bipolar transistor (HBT) processes.

K-band receiver front-ends in a GaAs metamorphic HEMT process

In this paper, we present K-band receiver blocks fabricated in a state-of-the-art 0.18-/spl mu/m GaAs metamorphic high electron-mobility transistor (MHEMT) process using a 60% indium-content InGaAs channel. Several circuits are developed to demonstrate the superior noise performance and successful integration of K-band receiver components in such a process. We show a low-power three-stage low-noise amplifier (LNA) with a gain of 23 dB and a noise figure (NF) of less than 1.6 dB at 30 GHz. This LNA shows InP-like performance on a GaAs substrate with a high RF yield of 84%. This is the first report of a statistical yield analysis of an MHEMT integrated circuit. We also demonstrate on-chip integration of a single-stage amplifier with a diode subharmonic mixer for low-power and broad-band receiver performance. This down-converter exhibits a conversion loss of 3 dB, overall NF of 5 dB, and third-order input intercept point of -5 dBm from 26 to 30 GHz.

Novel DC-offset cancellation techniques for even-harmonic direct conversion receivers

We present two novel dc-offset cancellation techniques for antiparallel diode pair even-harmonic mixers in a direct conversion receiver. Using fundamental equations, we describe the contribution of diode mismatch to dc offset and present an intrinsic mechanism of dc-offset cancellation. Similarly, we describe an extrinsic method of cancellation utilizing the second harmonic of the local oscillator. The cancellation techniques are successfully incorporated in fully monolithic C-band direct conversion receivers and mixers. Measurements confirm the equations and verify complete cancellation using the proposed methods. This works provides a solid foundation for the design and development of fully monolithic and high-performance direct conversion receivers.

A novel dc-offset cancellation technique for even-harmonic direct conversion receivers

We present a novel dc-offset cancellation technique in antiparallel diode pair even-harmonic mixers for direct conversion receivers. Using fundamental equations we describe the contributions of diode mismatch to dc-offset and present a novel method for dc-offset cancellation using the 2/sup nd/ harmonic of the LO. Measurements confirm the equations and verify complete dc-offset cancellation using the proposed method.

Development of IEEE802.11a WLAN LNA in silicon-based processes

We describe the effects of substrate parasitics in silicon-based processes and present a methodology for designing low-noise amplifiers (LNAs) in silicon processes. Our techniques resulted in excellent agreement between simulations and measurements for a test case LNA design for 802.11a. This LNA, which covers 5-6 GHz and has gain switching is designed in a 0.8 μm SiGe bipolar technology with f/sub T/ of 50 GHz. The LNA exhibits a gain of more than 24 dB in the 5-6 GHz band with a noise figure (NF) less than 2.5 dB. The agreement between simulation and measured data is demonstrated.

GaAs MESFET-based MMIC VCO with low phase noise performance

We present a fully monolithic X-band MMIC VCO implemented in a GaAs MESFET process. Measurement results demonstrate a single sideband phase noise ratio of -91 dBc/Hz at a 100 KHz offset. This VCO achieves a maximum output power of 11.5 dBm with 550 MHz of frequency tuning range. The output power can be controlled over 12 dB while maintaining excellent phase noise. Second harmonic suppression of 20 dB or more is measured across the entire power and frequency range. This result is comparable to, or better than, the best reported result of VCOs implemented in HEMT and HBT processes.

A compact monolithic C-band direct conversion receiver

A compact monolithic C-band direct conversion receiver has been implemented in a commercial 0.6 μm GaAs MESFET process. Subharmonic mixing is utilized to suppress even-order intermodulations and eliminate DC offsets. Second-order input intercept point (IIP2) of +17 dBm, third-order input intercept point (IIP3) of +8 dBm, and DC offset of -80 dBm are measured on wafer without the use of additional off-chip components. This receiver occupies a die area of 35×53 mil2 and operates on 2.7 V with 21 mA of DC current. This is the first demonstration of a C-band direct conversion receiver MMIC with excellent linearity, DC offset, and DC power consumption.

A 5.8 GHz OFDM GaAs MESFET MMIC chip set

This paper presents the implementation of a 5.8 GHz GaAs MESFET MMIC transceiver chip set compatible with the OFDM standard. The receiver is designed for low noise figure and high IIP3. The transmitter is designed to satisfy high peak-to-average power ratio. This design matches closely with the requirements for 5.8 GHz wireless LAN applications. To the best of our knowledge, this research represents the first reported implementation of the OFDM standard at 5.8 GHz.

A K-band subharmonic down-converter in a GaAs metamorphic HEMT process

In this paper, we present the first implementation of a K-band subharmonic down-converter fabricated in a 0.18-/spl mu/m GaAs Metamorphic High Electron Mobility Transistor (MHEMT) process. The low noise and high gain characteristics of the MHEMTs at K-band allow for the integration of a single-stage amplifier with a subharmonic mixer resulting in low-power broadband performance. The subharmonic mixer exhibits conversion loss of 13 dB and IIP3 of +8 dBm from 23 to 30 GHz. With the addition of the amplifier, the down-converter exhibits a conversion loss of 3 dB, noise figure of 5 dB, and IIP3 of -5 dBm from 26 to 30 GHz. The single-stage amplifier exhibits InP-like performance with gain of 11 dB, NF of 1.5 dB, and dc power consumption of 15 mW.