C. Chun

Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits

In this paper, we present integrated circuit solutions that enable high-speed data transmission over legacy systems such as short reach optics and electrical backplanes. These circuits compensate for the most critical signal impairments, intersymbol interference and crosstalk. The finite impulse response (FIR) filter is the cornerstone of our architecture, and in this study we present 5- and 10-Gsym/s FIR filters in 2-/spl mu/m GaAs HBTs and 0.18-/spl mu/m CMOS, respectively. The GaAs FIR filter is used in conjunction with spectrally efficient four-level pulse-amplitude modulation to demonstrate 10-Gb/s data throughput over 150 m of 500 MHz/spl middot/km multimode fiber. The same filter is also used to demonstrate equalization and crosstalk cancellation at 5 Gb/s on legacy backplane. The crosstalk canceller improves the bit error rate by five orders of magnitude. Furthermore, our CMOS FIR filter is tested and demonstrates backplane channel equalization at 10 Gb/s. Finally, building blocks for crosstalk cancellation at 10 Gb/s are implemented in a 0.18-/spl mu/m CMOS process. These circuits will enable 10-Gb/s data rates on legacy systems.

Equalization and near-end crosstalk (NEXT) noise cancellation for 20-Gb/s 4-PAM backplane serial I/O interconnections

Limitations in current backplane environments impede high-speed data transmission above 5 Gb/s. A system architecture to extend the transmission capacities of legacy backplanes is proposed. The incentives for using a four-level pulse amplitude modulation (4-PAM) scheme are also presented. The architecture is built from feed-forward equalizer and tunable filter elements for near-end crosstalk noise cancellation. Each of the circuits is implemented in a standard 0.18-/spl mu/m CMOS process. The building blocks of the architecture, which include an LC ladder, a modified Gilbert-cell multiplier with improved headroom, and a tunable active high-pass filter are described in detail. Results of the architecture are shown demonstrating 20-Gb/s 4-PAM signal transmission.

Development of microwave package models utilizing on-wafer characterization techniques

A package characterization technique using coplanar waveguide (CPW) probes and line-reflect-match (LRM) calibrations for surface-mountable packages is presented. CPW-to-package adapters (CPA) are fabricated on alumina substrates to mount and measure the high-frequency response of plastic packages. Offset CPA standards in conjunction with an LRM calibration are used to de-embed the response of the adapters from the measured S-parameters. Application of this method is demonstrated by characterizing and modeling surface-mount microwave plastic packages.

Two-dimensional 8/spl times/8 photoreceiver array and VCSEL drivers for high-throughput optical data links

Two custom GaAs integrated circuits (ICs) have been developed for enabling vertical cavity surface emitting laser (VCSEL) arrays to be used for high throughput spatial division multiplexed (SDM) optical data links. A 16-channel driver IC was developed to drive the VCSEL array and an 8/spl times/8 monolithic photoreceiver, which spatially matches the VCSEL array, was developed for receive. Both of these circuits were fabricated in a standard commercial GaAs MESFET process with parasitic photodetectors used for the photoreceivers. Power dissipation and circuit size were primary design challenges for both circuits. The present 8/spl times/8 array size along with an estimated usable channel speed of 1 Gb/s allows for an aggregate throughput of 64 Gb/s.

A novel dc-offset cancellation technique for even-harmonic direct conversion receivers

We present a novel dc-offset cancellation technique in antiparallel diode pair even-harmonic mixers for direct conversion receivers. Using fundamental equations we describe the contributions of diode mismatch to dc-offset and present a novel method for dc-offset cancellation using the 2/sup nd/ harmonic of the LO. Measurements confirm the equations and verify complete dc-offset cancellation using the proposed method.

Thin film pseudomorphic AlAs/In/sub 0.53/Ga/sub 0.47/As/InAs resonant tunnelling diodes integrated onto Si substrates

We report high peak-to-valley current ratio (PVR) resonant tunneling diodes (RTDs) bonded to silicon. Pseudomorphic AlAs/In/sub 0.53/Ga/sub 0.47/As/InAs resonant tunneling diode structures grown on semi-insulating InP with peak-to-valley current ratios as high as 30 at 300 K have been separated from the growth substrate and bonded to silicon substrates coated with Si/sub 3/N/sub 4/, forming thin film devices. In addition, thin film multiple stack RTD structures have been bonded to silicon substrates. The I-V characteristics of both the single and multi-stacked thin film RTDs exhibit no signs of degradation after bonding to the host substrate. These results are the first successful demonstration of InP based electronics bonded to a silicon host substrate and enable the integration of RTDs with conventional silicon circuitry.

A 0.18/spl mu/m CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels

In this paper, we present a 20 Gbps throughput PAM-4 analog feed forward equalizer with a newly proposed multiplier cell. The conventional Gilbert-cell multiplier is modified to achieve enough voltage headroom for 0.18/spl mu/m standard CMOS process while maintaining high-speed characteristics. Pulse amplitude modulation (PAM)-4 is adopted to increase the overall data throughput over bandwidth limited channel. For the tap delay line implementation, a passive L-C ladder topology is used, which enables fractional symbol tap spacing while maintaining the bandwidth required for 20 Gbps PAM-4 signal. The overall architecture is implemented using 0.18 /spl mu/m, standard CMOS process with 1.8V supply voltage. The 20 Gbps PAM-4 signal is received through the backplane channel, and the signal impairment is successfully compensated through the fabricated FFE.

Surface mount microwave package characterization technique

We present a plastic package characterization technique using coplanar waveguide to package adapters (CPA) and line-reflect-match (LRM) calibrations. LRM calibrations on off-set CPA standards are employed to de-embed the response of CPA adapters in measured S-parameters. A variety of small shrink outline packages (SSOP) has been characterized to 26.5 GHz using this technique.

Fully integrated 0.18/spl mu/m CMOS equalizer with an active inductance peaking delay line for 10Gbps data throughput over 500m multimode fiber

In this paper, we present a fully integrated equalizer for 10Gbps data throughput over multimode fiber. The equalizer uses a newly proposed active delay line approach with an active inductance. The active inductance enables 10Gbps data throughput equalization with an integrated single to differential converter. A buffer stage is also integrated at the output stage to deliver low voltage differential signaling (LVDS) level at the 50-ohm termination. The overall architecture is implemented using a 0.18/spl mu/m, standard CMOS process with a 1.8V supply voltage. The active delay line scheme results in reduced equalizer chip area in comparison to a passive delay line approach. The 10Gbps non return-to-zero (NRZ) signal is received through a 500m multimode fiber channel, and the signal impairment due to the differential mode delay is successfully compensated.

InP HBT on Si substrates with integral passive components: a wafer scale package

An InP based HBT is integrated to a Si substrate insulated with BCB by removing the InP substrate and bonding the active device layers. The DC and RF characteristics show minimal degradation after bonding to the Si. Transmission line structures are fabricated and measured on both bare Si and Si coated with BCB. Insertion loss of the CPW lines demonstrate useful high frequency propagation with BCB on the lossy substrate. Utilizing these results, an amplifier is designed to demonstrate InP thin-film integrated high frequency circuits on silicon. These results point to the development of wafer scale packaged high frequency electronics.