Barry Sassman

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation

Using a presilicide implantation approach, we demonstrate that the Schottky barrier height (SBH) of NiSi/n-Si(100) can be modulated by doping a Si substrate with a halogen species such as chlorine. Activation energy measurements indicate that an ultralow barrier of 0.08 eV for NiS/n-Si can be achieved when a high dose (~1 times 1015 cm2) of chlorine is implanted prior to Ni silicidation. A secondary ion mass spectroscopy analysis on the presilicide Cl-implanted NiSi shows chlorine segregates at the interface with SBH tuning from 0.68 to 0.08 eV on n-Si and a corresponding increase in hole SBH on p-Si(100). The presilicide Cl-implanted NiSi film also demonstrates an enhanced thermal stability with a low sheet resistively of < 28 muOmega even up to 850degC.

Demonstration of

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (<i>L</i> _g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (<i>I</i> _on/<i>I</i> _off) ratio (~5times10⁴ 55-nm <i>L</i> _g). The intrinsic gate delay of these heterostructures is ~3 ps at <i>I</i> _on/<i>I</i> _off~10⁴. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short <i>L</i> _g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

L_{g} \sim \hbox{55}\ \hbox{nm}

We report on the plasma induced damage in the TiN/HfSiO/sub 4/ gate stack, and, specifically, its impact on pMOSFETs. Plasma assisted deposition processes after the gate stack etch step appear to cause most plasma damage, manifested by greater degradation of the plate antenna structures (area intensive) compared to comb antennas (perimeter intensive). The transient charge trapping behavior of the HfSiO/sub 4/ film seems to prevent destructive dielectric breakdown. Electrical stress could generate additional traps in the film damaged by the plasma process.

pMOSFETs With

We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k and metal gate stack. These attributes taken together constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.

\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}

Plasma-based dry etch is used as the industry standard gate etch in conventional CMOS fabrication flow. However, past studies indicate that plasma-induced dry etch may impact device performance. The current research trend toward replacing conventional silicon dioxide and polysilicon gate stacks with high-k/metal gate stacks introduces a new challenge: development of new dry etch processes for critical new metals and their alloys. In this letter, a comparative study in the context of device performance has been conducted to compare dry etch versus wet etch for gate stack etch of hafnium oxide/tantalum silicon nitride gate stack. It has been found that the dry-etched gate stack exhibit significantly more gate leakage current and poorer uniformity in threshold-voltage distribution

Channels, High

Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate- source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32 nm technology node and beyond.

I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})

We report a comprehensive study of surface orientation, channel direction, and uniaxial strain technologies for SiGe channels CMOS. On a (110) surface, SiGe nMOS demonstrates a higher electron mobility than Si (110) nMOS. The hole mobility of SiGe pMOS is greater on a (110) surface than on a (100) surface. Both electron and hole mobility on SiGe (110) surfaces are further enhanced in a <110> channel direction with appropriate uniaxial channel strain. Results obtained in this work advance the integration technique of high mobility CMOS on a single SiGe (110)<110> channel orientation to enhance overall performance without the process complexity associated with hybrid channel CMOS approaches.

, and Controlled Short Channel Effects (SCEs)

We report on new observations of hot carrier (HC) degradation in strained Si/Si1-xGex(x = 0.2 to 0.5) p-MOSFETs. By using low voltage current-voltage measurement coupled with carrier separation, we are able, for the first time, to easily distinguish the energy distribution of the interface traps. High-K dielectrics on SiGe p-channel show higher interface traps generation located close to conduction band under channel hot carrier stressing and uniform interface trap under drain avalanche hot carrier stressing, both of which can be mitigated by increasing Ge% in the Si/SiGe channel. Detailed study on Si capping layer (les 20 Aring) shows good immunity against Drain Avalanche Hot Carrier but is degraded under Channel Hot Carrier stressing. The results suggest that higher Ge% and thinner Si cap is preferably for hot carrier reliability for low voltage application with 10 yrs lifetime at operating voltage of -0.85 V.

Impact of plasma induced damage on pMOSFETs with TiN/Hf-silicate stack

For the first time, a set of complementary metal oxide semiconductor (CMOS) FinFET devices with two different high-k/metal gate stacks of dual work function has been integrated on the same wafer to overcome the integration complexity. Two completely different metals deposited by atomic layer deposition have been integrated in a process that includes gate stack integration and dual metal gate etch. Excellent short channel characteristics with low drain induced barrier lowering (DIBL) and subthreshold swing DeltaSS have been observed with fairly symmetric VTh.