Se-Hoon Lee

Demonstration of

High-performance sub-60 nm Si/SiGe (Ge:~75%)/Si heterostructure quantum well pMOSFETs with a conventional MOSFET process flow, including gate-first high-kappa/metal gate stacks with ~1 nm equivalent oxide thickness, are demonstrated. For the first time, short gate length (<i>L</i> _g) devices demonstrate not only controlled short channel effects, but also an excellent on-off current (<i>I</i> _on/<i>I</i> _off) ratio (~5times10⁴ 55-nm <i>L</i> _g). The intrinsic gate delay of these heterostructures is ~3 ps at <i>I</i> _on/<i>I</i> _off~10⁴. OFF-state leakage was minimized by controlling the defects in the epitaxial films. Finally, these short <i>L</i> _g devices, when benchmarked against state-of-the-art Si channel pMOSFETs, appear to be very promising in replacing the Si channel in CMOS scaling.

L_{g} \sim \hbox{55}\ \hbox{nm}

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

pMOSFETs With

Preserving the integrity (e.g., Ge concentration, strain, and lattice perfection) of pseudomorphically grown silicon germanium (SiGe) heterostructure channels on Si substrates is one of the most critical factors in obtaining optimal pMOSFET performance from high hole mobility of strained SiGe. A millisecond Flash-assisted rapid thermal annealing (RTA) technique was applied to source/drain (S/D) dopant activation of high-Ge-concentration SiGe channel MOSFETs with a high-k/metal gate stack. Flash annealing of SiGe channel pMOSFETs is shown to be an effective way to preserve channel integrity while achieving a low S/D resistance. Excellent mobility and short-channel device performance are realized. In addition, as the concentration of Ge in the SiGe layer is increased, high B activation can be achieved with a lower peak temperature Flash anneal. As a result, the sheet resistance of the implanted p+ junction can be comparable with that of higher temperature Flash-annealed (or optimal spike-annealed) Si. Furthermore, minimizing Ge diffusion reduces performance variation (such as statistical threshold voltage variation), which may be caused by the introduction and/or growth of defects in the strained SiGe heterostructure channel. It is shown that high-performance SiGe channel pMOSFETs with high Ge concentrations and a scaled high- k/metal gate can be achieved by a millisecond Flash-assisted RTA technique while preventing undesirable effects in the SiGe channel, such as within-wafer statistical performance variation.

\hbox{Si/Si}_{0.25}\hbox{Ge}_{0.75}/\hbox{Si}

Quantum well (QW) FETs with compressively-strained SiGe channel are promising candidates for pMOSFET for future logic technology with scaled operating voltage [1–3]. High hole mobility observed in strained SiGe channel layer, as compared to Si, is expected to result in enhanced performance of these devices for deep submicron channel lengths. However, most of experimental results in literature so far, focusing on [011] channel direction on relaxed (100) Si bulk substrate have shown mobility degradation (hence drive current degradation) or marginal drive current enhancement at short channel regime in pseudomorphic SiGe based channels over Si control [4–7]. This has been attributed to effects of additional Coulomb scattering (from Nit and halo) and from neutral defects [4], as shown in Fig. 1. While these are indeed additional source of defects over Si counterpart inhibiting performance enhancement, highly anisotropic hole band structure with biaxial compressive strained SiGe channel could also play an important role on the ON-state performance degradation especially in deep submicron regime. In this paper we investigate the channel orientation dependence on the performance in an optimized Si0.5Ge0.5 QW channel. Strong drive current (mobility) enhancement is observed in [010] versus [011]. This directional dependence is further amplified at shorter channel lengths and lower temperature, and is explained on the basis of anisotropy in band structure.

Channels, High

Shallow junctions formed on thin Ge-on-Si heterostructures are characterized in this paper. The reverse leakage current showed a strong dependence on the Ge thickness, which is believed to be due to the different activation temperature of ions implanted in the Ge layers and in the Si substrates. Ge pMOSFETs fabricated on thin Ge layers showed more significant improvement in short channel effects (SCEs) and subthreshold swing (SS) characteristics than those on thick Ge layers. Ge pMOSFETs on thin Ge are a very promising device structure for future technology nodes because of their superior immunity to short channel effects and potential drivability due to their high mobility channel.

I_{\rm on}/I_{\rm off}\ (≫ \hbox{5} \times \hbox{10}^{4})

MOSFETs were fabricated on both thick and thin epi SiGe films. An ultra thin (~ 1- 2 nm) epi Si cap grown on the SiGe layers serves to separate the Ge from the high k dielectric as well as form a SiO2 interfacial layer between the SiGe channel and the high k gate dielectric. There is evidence that this cap layer is completely oxidized during the ozone based ALD high k deposition process. Both epitaxial Si as well as SiO2 based capping layers are reported to improve the interface for pure Ge devices. PMOSFETs were fabricated using a conventional 4 mask step process flow using a deposited field isolation oxide, ALD high k, metal gate electrode and implanted source/drain regions.

, and Controlled Short Channel Effects (SCEs)

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

ON-State Performance Enhancement and Channel-Direction-Dependent Performance of a Biaxial Compressive Strained Si 0.5 Ge 0.5 Quantum-Well pMOSFET Along 110 and 100 Channel Directions

To increase channel mobility beyond Sis physical limits, Ge is being intensively investigated as high- mobility channel material for potential high-speed circuit applications. Ge pMOSFETs have been demonstrated with an hole mobility enhancement by using stained or relaxed Ge-on-Si heterostructures. One of the issues, however, is the uncontrolled (normally positive) threshold voltages (Vt), which must be tuned to low negative values for CMOS applications. In this study, we investigate dependence of Vt shift on epi-Ge thickness, channel doping, and Si cap layers. The Vt shift is attributed to combined effect of Ge and Si properties in heterostructures.

Impact of Millisecond Flash-Assisted Rapid Thermal Annealing on SiGe Heterostructure Channel pMOSFETs With a High-k/Metal Gate

pMOSFET performance of high Ge content (~50%) biaxial compressive strained SiGe heterostructure channel pMOSFETs is characterized, and performance between 〈110 〉 and 〈100 〉 channel orientations on a (001) substrate is compared for physical channel lengths down to ~80 nm. Temperature-dependent mobility and velocity are characterized for both channel directions. First, it is shown that high Ge content SiGe-based channels can deliver drive current enhancement over unstrained Si below sub-100-nm channel lengths. Second, it is found that, with a higher Ge content SiGe channel under biaxial compressive strain, there is a difference of drive current between 〈110 〉 and 〈100 〉 channel directions, and the difference increases when temperature is lowered and/or when channel length is scaled down. An external series resistance difference is detected between two channel directions, although it appears to be insufficient to explain all the direction-dependent drive current difference. Channel transport behavior in different channel orientations can be clearly observed with low external source/drain (S/D) series resistance achieved with a millisecond S/D dopant activation anneal process while controlling the thermal budget. Two possibilities have been investigated to understand channel-direction-dependent performance: possible differences in effects of device processing impact between two channel directions and anisotropic transport effects from an anisotropic hole band structure, particularly under biaxial compressive strain in a SiGe channel pseudomorphically grown on a Si substrate.

Hole band anisotropy effect on ON-state performance of biaxial compressive strained SiGe-based short channel QW pMOSFETs: Experimental observations

We investigate boron transient enhanced diffusion (TED) and series resistance in SiGe/Si heterojunction channel pMOSFET. The stress gradient at the SiGe/Si interface near the gate edge in high Ge concentrations are found to determine boron TED as well as extension junction shape, which has a significant impact on the parasitic LDD and source/drain (S/D) series resistance. In addition, high Ge concentrations in the epitaxial SiGe layer on top of Si substrate result in a high sheet resistance during a 1000°C/5s rapid thermal processing (RTP), which is mainly due to alloy scattering and interface roughness scattering.