Bart Degroote

Solid phase epitaxy versus random nucleation and growth in sub-20nm wide fin field-effect transistors

The authors investigate the implications of amorphizing ion implants on the crystalline integrity of sub-20nm wide fin field-effect transistors (FinFETs). Recrystallization of thin body silicon is not as straightforward as that of bulk silicon because the regrowth direction may be parallel to the silicon surface rather than terminating at it. In sub-20nm wide FinFETs surface proximity suppresses crystal regrowth and promotes the formation of twin boundary defects in the implanted regions. In the case of a 50nm amorphization depth, random nucleation and growth leads to polycrystalline silicon formation in the top ∼25nm of the fin, despite being only ∼25nm from the crystalline silicon seed.

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.

Step decoration and surface alloying: growth of cobalt on Ag(100) as a function of deposition temperature

The temperature dependence of the growth of cobalt on Ag(100) has been studied with scanning tunneling microscopy. For submonolayer coverage, the preferred sites of nucleation change with increasing temperature from a random distribution over the terraces to decoration of the silver steps on the upper side. Because of the step decoration, the silver surface, which has propagating steps at elevated temperatures, is frozen into a stable configuration. Numerical analysis of island densities gives an estimation of 0.6(2) eV for the diffusion barrier for cobalt on Ag(100). Higher deposition temperatures result in the formation of a surface alloy. For higher coverages, however, high-temperature deposition or post-annealing after room-temperature deposition does not lead to a cobalt film completely covering the silver surface, but to the formation of clusters embedded in irregular-shaped silver terraces. An explanation is given in terms of a competition between the surface free energy and the heat of mixing.

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Multiple gate field effect transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit

Step decoration during deposition of Co on Ag(001) by ultralow energy ion beams

A possibility for decorating atomic steps on single-crystal surfaces by using ultralow energy ion beams is reported. Isotopically pure ion beams are produced by a mass separator and subsequently decelerated by an electrostatic lens. The lens was designed to allow sweeping of the ion beam in order to obtain a uniform deposition over a large area. The preferred sites of single Co atoms on Ag are investigated with in situ scanning tunneling microscopy measurements. A clear indication is found that by increasing the energy of the deposited Co to several electron volts, an enhanced Co decoration of the Ag steps is induced. This technology opens perspectives for an increasing number of elements which can form self-organized nanostructures such as atomic wires on vicinal crystal surfaces.

Quantitative characterization of the surface morphology using a height difference correlation function

A height difference correlation function was defined for the analysis of experimentally obtained real space images of a surface morphology. Using scanning tunneling microscope images of two different surfaces, the Si(111)-7×7 reconstruction and hyperthermally deposited thin Co films on Si(111), we demonstrate the advantages of this characterization procedure. Parameters such as the grain size and the roughness at short length scale, which are difficult to determine, especially for surfaces exhibiting randomly distributed closely packed grains, can be easily obtained from an appropriate fit of the height difference correlation function. This fit, based on the theory of kinetic roughening, simultaneously provides quantitative information on the roughness at short (Hurst parameter) and large length scales and surface in-plane correlation length of the film. The results for the overall surface roughness are consistent with the values which can be directly obtained from scanning tunneling microscope measuremen...

Misoriented domains in (0001)-GaN/(111)-Ge grown by molecular beam epitaxy

Structural characterization has been performed on (0001)-GaN epilayers grown on (111)-Ge substrates using plasma assisted molecular beam epitaxy. By combining high-resolution x-ray diffraction, transmission electron microscopy, and scanning transmission electron microscopy, it has been shown that the GaN epilayer consists of misoriented domains. The domains are rotated about the GaN-[0001] (Ge-[111]) zone axis by 8° with respect to each other and by ±4° with respect to the Ge substrate. These domains need to be eliminated to reduce grain boundary defects and improve GaN crystal quality.

Integration challenges for multi-gate devices

The FinFET transistor is the most widely studied and known multi-gate architecture that has the potential to be scaled to beyond the 45 nm technology node. In this paper a number of integration issues have been addressed. In first section the patterning challenges have been discussed. Due to the particular layout of the FinFET devices a variation in fin width is seen due to the rounding of the fin opening. This problem can be addressed by looking at alternative litho settings and OPC. Next to that topography plays an important in patterning the gate. It is seen that the optimization of the different OE times is key in achieving a controlled gate profile without poly residues. Techniques like poly etch-back can be used to alleviate the topography issues as much as possible. Threshold voltage tuning with implantation is extremely difficult for narrow fin devices. Workfunction tuning by either deposited metal gate or full silicidation is seen as a more viable solution. The extensions and deep source/drain areas need to be as conformal as possible in order to avoid the dominance of the top channel over the sidewalls. However, conventional implantation techniques are unsuitable and alternative implantation techniques need to be investigated. Next to that, when high density is needed, the fin spacing will limit the allowed tilt angle due to implant shadowing. The sidewall crystal orientation is different from that of the top channel and this will impact the mobility of holes and electrons in a different way. Rotation of the fins over 45 degrees, the use of strained layers and strained SiGe source/drain have been briefly discussed as possible solutions to tackle this problem. Finally, the impact of the fin width on R/sub SD/ has been shown. Elevated source/drain has been brought forward as a solution to this problem.

Optimization of low temperature silicon nitride processes for improvement of device performance

This paper gives some insights in the applications where PECVD nitrides can be introduced to replace the LPCVD layers and how the process parameters need to be varied to obtain the desired properties. Film properties like stress, hydrogen content, wet etch rate and deposition rate are reported. The nitrides are optimized for specific applications and examples on the influence of nitride properties on device performance are given. It is important to investigate that the advantage of the high film integrity of nitride layers used in the past is not lost due to the strong demand for developing new process schemes with low thermal budget layers. We show that PECVD films are a valid alternative for LPCVD and that the majority of the film properties satisfy the criteria to use PECVD films as contact-etch-stop layers, silicidation blocking films and spacer materials.