A. Dixit

Analysis of the parasitic S/D resistance in multiple-gate FETs

The multiple-gate field-effect transistor (FET) is a promising device architecture for the 45-nm CMOS technology node. These nonplanar devices suffer from a high parasitic resistance due to the narrow width of their source/drain (S/D) regions. We analyze the parasitic S/D resistance behavior of the multiple-gate FETs using a novel, S/D geometry-based analytical model, which is validated using three-dimensional device simulations and experimental results. The model predicts limits to parasitic S/D resistance scaling, which reveal that the contact resistance between the S/D silicide and Si-fin dominates the parasitic S/D resistance behavior of multiple-gate FETs. It is shown that the selective epitaxial growth of Si on S/D regions alone may be insufficient to meet the semiconductor roadmap target for parasitic S/D resistance at the 45-nm CMOS technology node.

Impact of Line-Edge Roughness on FinFET Matching Performance

As a result of CMOS scaling, the critical dimension (CD) of integrated circuits has been shrinking. At sub-45 nm nodes, in which FinFET is a viable device architecture, line-edge roughness (LER) in current Si-based technologies forms a significant fraction of the line CD. In such cases, analyzing the impact of LER on FinFET performance is vital for meeting various device specifications. The impact of LER on the matching performance of FinFETs is investigated through statistical device simulations, comparing the relative importance of fin- and gate-LER. Fin-LER is shown to significantly degrade FinFET matching performance under DC and transient operations. Combining our device simulation results with experimental data, it is shown that fin-LER will dominate the intra-bit-cell stochastic mismatch in FinFET static random access memories at the LSTP-32-nm node. The electrical performance of spacer-defined fin (SDF) and resist-defined fin (RDF) patterning technologies has been compared. It is shown that, with respect to RDF patterning, the spacer-defined process has the potential to improve FinFET matching performance by 90%.

Impact of LER and Random Dopant Fluctuations on FinFET Matching Performance

Parameter variations pose an increasingly challenging threat to the CMOS technology scaling. Among the sources of variability, line-edge-roughness (LER) and random dopant (RD) fluctuations are significant in current technology nodes. In this paper, the impact of the LER and RD on the matching performance of FinFETs is investigated for the LSTP-32 nm node, where these devices represent an attractive alternative to the planar CMOS transistors. Line-edge-roughness contributions from the fin, top-, and side wall-gates of n- and p-channel FinFETs are compared by means of 2-D and 3-D technology computer-aided design (TCAD) simulations, performed with a quantum-corrected hydrodynamic model on large statistical ensembles. Correlations between geometrical roughness and resulting electrical parameters are analyzed to provide further insight into the impact of the LER. A noise analysis approach is adopted to evaluate the impact of RD fluctuations throughout the impurity concentration ranges of interest, providing a direct comparison with the line-edge-roughness contributions. The impact of the extension doping profile specifications on the LER- and RD-induced mismatch is investigated, highlighting the potential drawbacks of junction engineering.

Multi-gate devices for the 32nm technology node and beyond

Due to the limited control of the short channel effects, the high junction leakage caused by band-to-band tunneling and the dramatically increased VT statistical fluctuations, the scaling of planar bulk MOSFETs becomes more and more problematic with every technology node. The ITRS roadmap predicts that from the 32 nm technology node on planar bulk devices will not be able to meet the stringent leakage requirements anymore and that multi-gate devices will be required. In this paper, the suitability of FinFET based multi-gate devices for the 32 nm technology and beyond will be discussed. Apart from the benefits, some technological challenges will be addressed.

A Low-Power Multi-Gate FET CMOS Technology with 13.9ps Inverter Delay, Large-Scale Integrated High Performance Digital Circuits and SRAM

This paper presents an in-depth analysis of digital performance of a Multi-Gate FET technology. Ring oscillators with metal gates and undopedfins show an inverter delay of 13.9ps at 1V, the highest performance of a Multi-Gate FET technology reported at 1.9nA off-current/stage. NAND and NOR show significant improvement in delay vs. stack height compared to bulk CMOS. SRAM cells and product-typical critical paths with more than 10k transistors demonstrate the capability for large-scale integration.

A functional 41-stage ring oscillator using scaled FinFET devices with 25-nm gate lengths and 10-nm fin widths applicable for the 45-nm CMOS node

In this letter, we have fabricated a functional FinFET ring oscillator with a physical gate length of 25 nm and a fin width of 10 nm, the smallest ever reported. We demonstrate that these narrow (W/sub fin/ = 10 nm) and tall (H/sub fin/ = 60 - 80 nm) fins can be reliably etched with controlled profiles and that they are required to keep the short-channel effects under control, resulting in drain-induced barrier leakage characteristics of 45 mV/V at V/sub dd/ = 1 V and L/sub g/ = 25 nm for the nFET. For these ultrathin (10 nm) fins, we have succeeded in properly setting the V/sub T/ at 0.2 V without the use of metal gates. In addition to ring oscillators, we also have obtained excellent pFET FinFET devices at wider fin widths (W/sub fin/ = 65 nm) with I/sub dsat/ = 380 /spl mu/A//spl mu/m at I/sub off/ = 60 nA//spl mu/m and V/sub dd/ = -1.2 V.

25% drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions

This paper shows, for the first time, the successful introduction of recessed, strained Si/sub 0.8/Ge/sub 0.2/ in the source and drain regions of pMOS MuGFET devices, improving the on-state current of these devices by 25%, at a fixed off-state condition. The improvement is shown to be a combined effect of compressive stress introduced along the channel, and of a reduced series resistance.

Impact of Stochastic Mismatch on Measured SRAM Performance of FinFETs with Resist/Spacer-Defined Fins: Role of Line-Edge-Roughness

Spacer-defined fin-patterning results in double/quadruple fin density and hence is attractive for high performance 32-nm CMOS applications. For the first time 55-nm gate-length FinFET SRAMs with resist- and spacer-defined fins are electrically compared. Due to short-range process variations, SRAM bit-cells with spacer-defined fins show approximately 2.5 times higher variability in static-noise-margin than resist-defined fins at VDD=1.2V. These SRAM test-cells achieve 130-nm planar-bulk comparable intra-bit-cell stochastic-mismatch and static noise margins

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

We demonstrate that for aggressively scaled FinFETs, with 2nm HfO 2 and TiN metal gate (i.e., workfunction close to midgap), several parasitic leakage mechanisms that impact the off-state current become dominant. We provide a detailed characterization of these mechanisms as well as design guidelines for eliminating them by careful junction dopant placement and S/D silicide engineering in order to achieve high Ion/Ioff ratios. Up to 20times GIDL reduction is achieved with minimum drive loss with asymmetric extensions. Using selective epitaxy on S/D, suppression of parasitic Schottky effects is also demonstrated resulting in a Ioff reduction of 10000times

Doubling or quadrupling MuGFET fin integration scheme with higher pattern fidelity, lower CD variation and higher layout efficiency

Multiple gate field effect transistors (MuGFET) with a fin pitch down to 50nm obtained with 193nm optical lithography and proposed fin quadrupling patterning method are demonstrated. The fins patterned with this technique feature improved CD control and line width roughness. High fin density in combination with Si-SEG that allows merging individual fins outside the spacer region lead to reduction in parasitic source/drain-resistance and 3-fold increase in drive current per surface unit