Devin Verreck

Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically.

Part I: Impact of Field-Induced Quantum Confinement on the Subthreshold Swing Behavior of Line TFETs

Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor nearby the gate dielectric. For an Si n-type TFET, the energy quantization in the conduction band is found to suppress the TAT through the interface-region traps by several orders of magnitude and delay the TAT through bulk traps nearby the gate dielectric with several hundreds of millivolts. The trap levels closer to the conduction band were found to be the most efficient for TAT in this n-TFET. The FIQC onset voltage shift in TAT through bulk taps is found to be smaller than the band-to-band tunneling (BTBT) shift, enhancing the effective SS degradation in TFETs. We therefore show that it is equally important to include the FIQC effect when calculating TAT as when calculating BTBT generation rates.

InGaAs tunnel diodes for the calibration of semi-classical and quantum mechanical band-to-band tunneling models

Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kanes formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance com...

Record performance InGaAs homo-junction TFET with superior SS reliability over MOSFET

InGaAs planar TFETs with 70% In content are fabricated and characterized. The increase of the In content of the 8 nm channel from 53% to 70% is found to significantly boost the performance of the device. Record performance I_on=4 μA/μm at I_eff = 100 μA/μm, V_dd=0.5V and V_d=0.3 V with minimum sub-threshold swing (SS_min) of 60 mV/dec at 300K is obtained for a homo-junction InGaAs device. Reliability assessment shows that the TFET SS and transconductance (g_m) are more immune to PBTI stress than its equivalent MOSFET device.

Uniform Strain in Heterostructure Tunnel Field-Effect Transistors

Strain can strongly impact the performance of III-V tunnel field-effect transistors (TFETs). However, previous studies on homostructure TFETs have found an increase in ON-current to be accompanied with a degradation of subthreshold swing. We perform 30-band quantum mechanical simulations of staggered heterostructure p-n-i-n TFETs submitted to uniaxial and biaxial uniform stress and find the origin of the subthreshold degradation to be a reduction of the density of states in the strained case. We apply an alternative configuration including a lowly doped pocket in the source, which allows to take full benefit of the strain-induced increase in ON-current.

InGaAs tunnel FET with sub-nanometer EOT and sub-60 mV/dec sub-threshold swing at room temperature

InGaAs homojunction Tunnel FET devices are demonstrated with sub-60 mV/dec Sub-threshold Swing (SS) measured in DC. A 54 mV/dec SS is achieved at 100 pA/μm over a drain voltage range of 0.2–0.5 V. The SS remains sub-60 mV/dec over 1.5 orders of magnitude of current at room temperature. Trap-Assisted Tunneling (TAT) is found to be negligible in the device evidenced by low temperature dependence of the transfer characteristics. Equivalent Oxide Thickness (EOT) is found to play the major role in achieving sub-60 mV/dec performance. The EOT of the demonstrated devices is 0.8 nm.

Perspective of tunnel-FET for future low-power technology nodes

Tunnel-FETs (TFETs) promise a subthreshold swing (SS) smaller than 60mV/dec and are considered as interesting candidates to replace MOSFET in future low-power technology nodes. The road ahead is challenging, with large discrepancy between experiment and prediction, the latter showing extremely promising performance for heterostructure TFET at small supply voltage Vdd. This paper starts with a calibration of the band-to-band tunneling (BTBT) models. It then discusses architecture and material optimizations, highlights the differences between n-TFET and p-TFET, and focuses on unexplored material aspects, like the decrease of dielectric constant with confinement. Parasitic effects are briefly touched upon, with trap-assisted tunneling (TAT) being the most challenging TFET parasitic to overcome. A new metric, VTAT, is defined to capture the TAT impact.

Can p-channel tunnel field-effect transistors perform as good as n-channel?

We show that bulk semiconductor materials do not allow perfectly complementary p- and n-channel tunnel field-effect transistors (TFETs), due to the presence of a heavy-hole band. When tunneling in p-TFETs is oriented towards the gate-dielectric, field-induced quantum confinement results in a highest-energy subband which is heavy-hole like. In direct-bandgap IIIV materials, the most promising TFET materials, phonon-assisted tunneling to this subband degrades the subthreshold swing and leads to at least 10× smaller on-current than the desired ballistic on-current. This is demonstrated with quantum-mechanical predictions for p-TFETs with tunneling orthogonal to the gate, made out of InP, In0.53Ga0.47As, InAs, and a modified version of In0.53Ga0.47As with an artificially increased conduction-band density-of-states. We further show that even if the phonon-assisted current would be negligible, the build-up of a heavy-hole-based inversion layer prevents efficient ballistic tunneling, especially at low supply vol...

Improved source design for p-type tunnel field-effect transistors: Towards truly complementary logic

Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFETs potential to obtain a sub-60 mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60 mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In0.53Ga0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60 mV/dec SS, with an on-curr...

Full-zone spectral envelope function formalism for the optimization of line and point tunnel field-effect transistors

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET.