Bartlomiej J. Pawlak

Boron diffusion in amorphous silicon and the role of fluorine

We demonstrate that boron diffuses at high concentrations during low-temperature thermal annealing in amorphous silicon pre-amorphized by germanium ion implantation. For a typical boron ultrashallow junction doping profile, concentrations as high as 2×1020 cm−3 appear to be highly mobile at 500 and 600 °C in the amorphous silicon region before recrystallization. In crystalline silicon at the same temperatures the mobile boron concentration is at least two orders of magnitude lower. We also show that boron diffusivity in the amorphous region is similar with and without fluorine. The role of fluorine is not to enhance boron diffusivity, but to dramatically slow down the recrystallization rate, allowing the boron profile to be mobile up to the concentration of 2×1020 cm−3 for a longer time.

Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

Ultra-shallow p+ junctions formed by solid phase epitaxial regrowth (SPER) have promise for sub-65 nm CMOS technologies. Due to above-equilibrium solid solubilities and minimal diffusion, such junctions can far outperform spike-annealed junctions in terms of resistance, abruptness, and depth. However, the low-temperature annealing does not dissolve the end of range defects creating concerns for junction leakage in the device. In this work, we show how SPER junctions can be optimized to meet the ITRS junction profile and low-power leakage requirements of the 45 nm CMOS node [International Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 2001)]. Diode leakage is shown to decrease with Ge amorphization depth and B dose and energy. Leakage is shown to increase dramatically with the background doping level. Increasing the regrowth, or post-annealing, thermal budget improves leakage and can be optimized to avoid deactivation. The inclusion of a preanneal does not affect t...

Doping fin field-effect transistor sidewalls: Impurity dose retention in silicon due to high angle incident ion implants and the impact on device performance

The three dimensional (3D) nature of a fin field-effect transistor (FinFET) structure creates new challenges for an impurity doped region formation. For the triple gate FinFET, both top and side surfaces require high levels of dopant incorporation to minimize access resistance. In this work, we investigate the use of conventional ion implantation for the introduction of impurities in this 3D silicon structure. Specifically, we evaluate sidewall impurity dose retention at various angles of incidence. The retention of dose is determined by (i) trigonometry of the implant angle in the 3D fin system, (ii) backscattering, and (iii) material properties of the target surface. Dose retention is most sensitive to the implant angle. For a fixed implant projected range, lighter ions are more likely to be ejected from the target. Thus, heavier ions are better for dose retention. The influence of sidewall dose retention on the electrical performance of fully depleted FinFETs was investigated by means of 3D device simu...

Chemical and electrical dopants profile evolution during solid phase epitaxial regrowth

Solid phase epitaxial regrowth (SPER) is a promising method for junction formation of sub-65 nm complementary metal–oxide–semiconductor technology nodes. This is mainly due to a high dopant activation level, easy control over electrical junction depth, excellent abruptness, and limited boron diffusion. In the present research we investigate in detail the activation process and the chemical profile change after SPER junction activation with respect to the regrowth temperature. We also obtain the electrically active profiles. We find that the process window for SPER between T=620 °C and T=740 °C offers the best activation level and has a dopant profile similar to the as-implanted. While increasing the regrowth temperature, we observe the gradual increase of the transient enhanced diffusion effect and formation of B trapping centers in the end-of-range (EOR) region. At temperatures as high as T=800 °C and T=850 °C the dopant activation beyond the original a-Si layer is observed and the high metastable B acti...

Optimisation of Junctions formed by Solid Phase Epitaxial Regrowth for sub-70nm CMOS

For the 70nm CMOS node, it is anticipated that conventional implantation and spike annealing approaches, even with pre-amorphisation and co-implantation, are unlikely to provide pMOS junctions consistent with the ITRS requirements. Here the junction performance is limited by equilibrium solid solubility. As laser annealing and in-situ doping techniques currently have unsolved integration problems, there is a renewed interest in using solid phase epitaxial regrowth (SPER) to form ultra-shallow metastable junctions. Such junctions have the potential to have an active dopant profile similar to the as-implanted profile. This offers above equilibrium solid solubility and abrupt profiles compatible with 70nm and even 45nm nodes. However there are concerns about residual defects, deactivation, diffusion and uniformity. In this paper we show how the Ge, F and B implant and SPER anneal can be optimised for abrupt, uniform and highly activated B junctions. There is latitude for higher doses and energies than conventional implants, however results show that this may lead to clustering causing enhanced deactivation and reduced mobility. We give attention to the probing issues involved in characterising partially annealed junctions. With this approach, p-type junctions having a sheet resistance of 265 ohms/sq and depth of 22nm are realised which are compatible with 70nm and potentially 45nm CMOS nodes.

Probing doping conformality in fin shaped field effect transistor structures using resistors

For scaling complementary metal oxide semiconductor devices toward the ITRS goals for the 32nm technology node and beyond, fin shaped field effect transistor (finFET)-based structures have shown immense potential due to their scalability by maintaining high drive current at scaled voltages and smaller gate dimensions. Due to the three-dimensional geometry of finFETs and the need to obtain identical lateral dopant profiles on the top and the sidewall of the fins, the classical doping strategies need to be reengineered as regular beam line implants would lead to large nonconformalities. The development of alternative doping processes such as plasma immersion doping requires the availability of methods to probe doping conformality. A methodology based on a dedicated resistor structure was developed, enabling the use of automated measurements to provide fast feedback on the degree of sidewall doping within different dies, across the wafer, and to study the wafer to wafer variation within a lot containing vari...

Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

The limits of using B or BF2 alone in forming ultrashallow junctions have been reached for the 90 nm CMOS generation. In this paper we evaluate the use of Ge and F co-implants to extend conventional implantation and spike anneal to the 65 nm CMOS technology node. In this work we show that the F co-implant can improve the abruptness of the B junction, while the single Ge usually degrades it. The use of Ge co-implanted with F gives the best junction abruptness - less than 5nm/decade. The best trade-off between junction depth (Xj) and sheet resistance (Rsheet) is achieved by deep Ge pre-amorphization and deep co-implantation of F. A comparison between slow and fast ramp-up is made. Significant improvement for the junction activation, its depth and abruptness is obtained by spike anneal with fast ramp-up for B junctions with Ge and F co-implantation.

Ultrashallow junctions formed by C coimplantation with spike plus submelt laser annealing

A leading candidate for the formation of the ultrashallow junctions needed for Lg⩽45nm devices is the combination of coimplantation of a diffusion-retarding species such as carbon with a high temperature, millisecond annealing process after the conventional spike annealing. C coimplantation with B+ for p-type metal-oxide semiconductor and P+ for n-type metal-oxide semiconductor combined with conventional spike annealing produces reduced junction depths and improved dopant activation and profile abruptness, compared to similar implants without the coimplanted species. Addition of submelt laser annealing may further improve junction activation, but the dominant impact is gate depletion reduction, in that way, delaying the need to introduce metal gates. Devices show that the overlap capacitance is reduced, consistent with the shallower junction depths and reduced lateral diffusion. The improved dopant activation manifests itself in reduced series resistance and improved Ion values. Finally, scanning spreadin...

Application of flash-assist rapid thermal processing subsequent to low-temperature furnace anneals

The substantial reductions in anneal times, such as in flash-assist rapid thermal processing (fRTP), place considerably more emphasis on the initial condition of the wafer, which may assume a greater role in the dictating diffusion product (Dt). Investigations have been conducted on the effect of low-temperature preanneals prior to fRTP on the extended defect nucleation and evolution and on boron activation. Czochralski grown n-type silicon wafers are preamorphized with 8 Ge+ ions at a constant dose of 1×1015cm−2 and then implanted with 1keV, 1×1015cm−2 B. Low-temperature furnace anneals are performed at 500°C for 30min and the wafers subsequently subjected to flash-assist RTP anneals in the range 1000–1300°C. Four-point probe measurements indicate that the low-temperature anneal results in higher sheet resistance values. Plan-view transmission electron microscopy, secondary-ion-mass spectrometry, and Hall-effect measurements revealed no substantial differences in defect structure, junction depth, or mobi...

Boron pocket and channel deactivation in nMOS transistors with SPER junctions

In this paper, we demonstrate the consequences of extension junction formation by low-temperature solid-phase-epitaxial-regrowth in nMOS transistors. Atomistic simulations, experimental device results, sheet resistance, and scanning spreading resistance microscopy data indicate that the high concentration of silicon interstitials associated with the end-of-range defect band promote the local formation of boron-interstitial clusters, and thus deactivate boron in the pocket and channel. These inactive clusters will dissolve after the high concentration silicon interstitial region of the end-of-range defect band has been annihilated. This nMOS requirement is in direct opposition to the pMOS case where avoidance of defect band dissolution is desired, to prevent deactivation of the high concentration boron extension profile.