Emek Yesilada

Advanced OPC Mask-3D and Resist-3D modeling

The objective of this paper is to extend the ability of a more stable overall process control for the 28 nm Metal layer. A method to better control complex 2D-layout structures for this node is described. Challenges are coming from the fact that the structures, which limit the process window are mainly of 2D routing nature and are difficult to monitor. Within the framework of this study the emphasis is on how to predict these process-window-limiting structures upfront, to identify root causes and to assist in easier monitoring solutions enhancing the process control. To address those challenges, the first step is the construction of a reliable Mask-3D and Resist-3D model. Advanced 3Dmodeling allows better prediction of process variation upfront. Furthermore it allows highlighting critical structures impacted by either best-focus shifts or by low-contrast resist-imaging effects, which then will be transferred non-linearly after etch. This paper has a tight attention on measuring the 3D nature of the resist profiles by multiple experimental techniques such as Cross-section scanning electron microscopy methods (X-SEM) and atomic force microscopy (AFM). Based on these measurements the most reliable data are selected to calibrate full-chip Resist-3D model with. Current results show efficient profile matching among the calibrated R3D model, wafer AFM and X-SEM measurements. In parallel this study enables the application of a new metric as result of the resist profiles behavior in function of exposure dose. In addition it renders the importance on the resist shape. Together these items are reflected to be efficient support on process optimization and improvement on the process control.

Inverse Lithography Technique for advanced CMOS nodes

Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPCTM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.

Device specific characterization of yield limiting pattern geometries by combining layout profiling with high sensitivity wafer inspection

This paper reports on a new approach to capture the impact of marginal pattern geometries on occurrence of systematic yield-limiting defects. Layout profiling and Hot-Spot checking techniques were used to mark new incoming device layout for regions that approached the known marginal pattern geometries at a varying degree of match quality. Further these regions were translated into inputs for advanced high-sensitivity wafer inspection tools of the Broadband Plasma family with Context Based Inspection capability. Finally specially prepared wafers for this device were exercised through high sensitivity targeted inspections to assess the defect occurrence at each of the regions picked based on layout profiling. Finally all the data was assimilated into an easy-to-interpret visual which shows where the printing margins are smallest on this device.

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted overexposure by wafer topography with technology node downscaling evolution [1], [2]. Starting from 2xnm technology nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer topography which can cause drastic pattern degradation [2], [3]. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a consequence, computational lithography solutions are currently under development in order to correct wafer topographical effects on mask [3]. For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer stack. In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC flow for chip scale mask correction is presented with quality and run time penalty analysis.

Full field lithographical verification using scanner and mask intrafieldfingerprint

Full chip verification has become a key component of the optical proximity correction (OPC) methodology over the last decade. Full field verification to catch cross-field effects based on scanner information is becoming increasingly important in lithography verification. Lithographic Manufacturing Check (LMC) performed with the Brion Tachyon engine, which is the industry reference tool, now provides the capability to predict wafer CD variations across the entire field through process windows. LMC is catching and reporting weak lithographic points having small process windows or excessive sensitivities to mask errors based on the simulation from models with ASML scanner specific parameters. ASML scanner intra-field information such as dose, focus, flare, illuminator map, aberration data or mask bias map can be integrated into the LMC run to create an across-field verification and can improve the accuracy of the prediction at different field locations. In this study we compare such across-field LMC verification with a reference LMC without any scanner specific data. Scanner information was loaded into the LMC model by using the Scanner Fingerprint File (SFF) functionality. Various across field LMC runs using scanner information have been performed and analysed to identify critical design hotspots or scanner drifts and compared with wafer measurement. Full field Tachyon LMC results on 40nm Poly and 28nm Metal1 layer are presented. The goal is to investigate the impact of mask, lens aberrations, illuminator, dose and focus map. This investigation includes wafer validation of the methodology on identified critical hot spots.

Model-based stitching and inter-mask bridge prevention for double patterning lithography

As EUV Lithography is not ready yet for sub-20nm node manufacturing, ArF immersion lithography must extend its capability. Among various double patterning techniques already explored, Litho-Etch-Litho-Etch (LELE) is one of the main streams considered today to continue scaling at 20nm and below. Our paper presents an application of a new OPC algorithm designed to ensure a successful double patterning process at 20nm node. A novel OPC technique was applied to 20nm contact and M1 layers. It is intended for both double and multi-patterning lithography technologies providing model based capability for concurrent correction of the split layouts ensuring a robust stitching overlap of the cut features and preventing inter-mask bridging. We have also developed an OPC verification methodology for DP failures due to dose, focus, mask and overlay errors. One of the most critical challenges of DP technology is: ensuring sufficient stitching of the cut design shapes and preventing a risk of inter-mask shape bridging. This problem is rapidly exacerbated by the overlay error. It is demonstrated that the new OPC algorithm results in enhanced stitching overlap and a good space control between inter-mask shapes, thus, minimizing DP process implications on circuit reliability.

Demonstration of an effective flexible mask optimization (FMO) flow

The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification. STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach. The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based approach.

Study of SRAF placement for contact at 45 nm and 32 nm node

At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the depth of focus starts to be very limited. Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field region of a Contact layer mask enforces the edges movement to stop very quickly. The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated after inverse lithography, it is important to know what their behavior is, in term of size and placement. In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us to establish the trends for size and placement of the SRAF. Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at 45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the complexity by adding additional SRAF.

Accurate mask model implementation in optical proximity correction model for 14-nm nodes and beyond

Abstract. In a previous work, we demonstrated that the current optical proximity correction model assuming the mask pattern to be analogous to the designed data is no longer valid. An extreme case of line-end shortening shows a gap up to 10 nm difference (at mask level). For that reason, an accurate mask model has been calibrated for a 14-nm logic gate level. A model with a total RMS of 1.38 nm at mask level was obtained. Two-dimensional structures, such as line-end shortening and corner rounding, were well predicted using scanning electron microscopy pictures overlaid with simulated contours. The first part of this paper is dedicated to the implementation of our improved model in current flow. The improved model consists of a mask model capturing mask process and writing effects, and a standard optical and resist model addressing the litho exposure and development effects at wafer level. The second part will focus on results from the comparison of the two models, the new and the regular.

Patterning critical dimension control for advanced logic nodes

Abstract. Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.