Baw-Ching Perng

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

20nm gate bulk-finFET SONOS flash

High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (TP equiv 10mus and TE equiv 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with DeltaVt > 4V and TP,E equiv 1 ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines

Plasma induced substrate damage in high dose implant resist strip process

In this communication we report our work on the ashing of post high dosage implant photoresist removal. Attention is focused on plasma damage to the silicon substrate, in addition to hard skin removal capabilities. An inductively coupled plasma (ICP) source is chosen for this study due to its capability of separate control of source and bias power, although our results are directly applicable to conventional plasma ashing facilities. Electrical data for both NMOS and PMOS devices are compared and correlated with the physical substrate damage, and suggestions for a residue-free process with minimum substrate damage are given.

Accurate in-line CD metrology for nanometer semiconductor manufacturing

The need for absolute accuracy is increasing as semiconductor-manufacturing technologies advance to sub-65nm nodes, since device sizes are reducing to sub-50nm but offsets ranging from 5nm to 20nm are often encountered. While TEM is well-recognized as the most accurate CD metrology, direct comparison between the TEM data and in-line CD data might be misleading sometimes due to different statistical sampling and interferences from sidewall roughness. In this work we explore the capability of CD-AFM as an accurate in-line CD reference metrology. Being a member of scanning profiling metrology, CD-AFM has the advantages of avoiding e-beam damage and minimum sample damage induced CD changes, in addition to the capability of more statistical sampling than typical cross section metrologies. While AFM has already gained its reputation on the accuracy of depth measurement, not much data was reported on the accuracy of CD-AFM for CD measurement. Our main focus here is to prove the accuracy of CD-AFM and show its measuring capability for semiconductor related materials and patterns. In addition to the typical precision check, we spent an intensive effort on examining the bias performance of this CD metrology, which is defined as the difference between CD-AFM data and the best-known CD value of the prepared samples. We first examine line edge roughness (LER) behavior for line patterns of various materials, including polysilicon, photoresist, and a porous low k material. Based on the LER characteristics of each patterning, a method is proposed to reduce its influence on CD measurement. Application of our method to a VLSI nanoCD standard is then performed, and agreement of less than 1nm bias is achieved between the CD-AFM data and the standards value. With very careful sample preparations and TEM tool calibration, we also obtained excellent correlation between CD-AFM and TEM for poly-CDs ranging from 70nm to 400nm. CD measurements of poly ADI and low k trenches are also reported, and both show good correlation to in-line CD-SEM results.

Application of optical CD metrology based on both spectroscopic ellipsometry and scatterometry for Si-recess monitor

Scatterometry is gaining popularity in recent years as it shows itself as a worthy contender among existing metrology systems. Scatterometry provides fast, accurate and precise profile information, which is valuable for in-line process control in production environment. Scatterometry applications widely adopted in IC fabs include poly gate ADI and AEI, and shallow trench isolation depth measurements. Recently, the mobility enhancement by compressive strain at source/drain is reported which improves greatly PMOS Idsat. In this work, we extend the application domain of scatterometry technology to two-dimensional recessed Si profile used in strained source and drain (SSD) structures. Complexity of SSD structures measurement by scatterometry requires the use of many parameters in modeling, which hinders a stable library setup. Our approach in circumventing this issue is to identify the most sensitive parameters first and then further reduce the number of variables through an effective medium approximation (EMA). This paper will discuss the preparation, experiments, and results of the scatterometry measurements. The extracted data have been compared with transmission electron microscopy results. Good correlation in depth and profile are observed. In addition, we have performed repeatability test and fault detection checks and the trend chart indicates that our methodology is very robust for in-line process monitor.

Application of spectroscopic ellipsometry-based scatterometry for ultrathin spacer structure

The scatterometry technology has been developed widely in the poly gate and resist patterning application for critical dimension (CD) process control. The advantages of this technology are good precision, short cycle time and multiple information outputs. To extend this application even further on spectroscopic ellipsometry (SE) based scatterometry, the spacer structure application becomes one promising goal. In this work, we use SE based scatterometry to demonstrate a two-dimensional profile of ultra thin spacer with post-etched structure as well as CD measurement of the spacer. A brief theory and measurement results taken by dense and isolate structure will be discussed in this paper. The cross-section of TEM and the spectra fitting by scatterometry are also collected at the same location and compared. It shows a high correlation between the two. Finally, an example of minispacer fault detection methodology and repeatability test on scatterometry is also presented to show the capability for volume production.

Planarization process of BPSG: Capillary vs. centrifugal/gravitational forces

Film planarization process, of importance in semiconductor IC manufacturing, results from mutual competition between three forces: capillary, viscous, and gravitation. In this communication we compare, using simple geometric arguments, the order of magnitudes between the capillary force and a generalized centrifugal/gravitational force acting perpendicular to the surface. For patterns of sub-micron dimension and conditions similar to BPSG reflow and photo-resist coating we found that, within instrumental accessibility, the centrifugal term is much smaller than the capillary term. We conclude that the centrifugal/gravitational forces affect global patterns, i.e., with dimension larger than 1000 micrometers , while the capillary force dominates the sub-micro leveling process.