Jyu-Horng Shieh

5nm-gate nanowire FinFET

A new nanowire FinFET structure is developed for CMOS device scaling into the sub-10 nm regime. Accumulation mode P-FET and inversion mode N-FET with 5 nm and 10 nm physical gate length, respectively, are fabricated. N-FET gate delay (CV/I) of 0.22 ps and P-FET gate delay of 0.48 ps with excellent subthreshold characteristics are achieved, both with very low off leakage cur-rent less than 10 nA/ /spl mu/m. Nanowire FinFET device operation is also explored using 3-D full quantum mechanical simulation.

20nm gate bulk-finFET SONOS flash

High-performance FinFET SONOS (silicon-oxide-nitride-oxide-silicon) flash cells with gate length down to 20nm have been fabricated and operated successfully on bulk-silicon substrate for the first time. A program/erase window of 2V has been achieved with high P/E speed (TP equiv 10mus and TE equiv 1ms), and a 1.5V window remained after 10 years at room temperature. Multi-level storage is also obtained with DeltaVt > 4V and TP,E equiv 1 ms. Operation voltages are not more than 7V in the two applications. Gate disturb issues are alleviated by applying an appropriate bias on unselected bit lines

Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography

For the first time, a novel hybrid SOI/bulk CMOS technology with 20nm gate length and low-leakage 1.3nm thick SiON gate dielectric has been developed for advanced SOC applications. 26% (for N-FET) and 35% (for P-FET) improvements of intrinsic gate delay (CV/I) at low gate leakage of 20-40A/cm/sup 2/ have been achieved over previous leading-edge 45nm node version, while maintaining the same sub-threshold leakage (100nA//spl mu/m). 10 times reduction of the leakage can be further modulated by a virtual back-gate control. Fine patterning with line pitch of 90nm by immersion lithography is demonstrated, which features 0.183/spl mu/m/sup 2/ 6T-SRAM cell for 32nm node on-trend scaling.

Accurate in-line CD metrology for nanometer semiconductor manufacturing

The need for absolute accuracy is increasing as semiconductor-manufacturing technologies advance to sub-65nm nodes, since device sizes are reducing to sub-50nm but offsets ranging from 5nm to 20nm are often encountered. While TEM is well-recognized as the most accurate CD metrology, direct comparison between the TEM data and in-line CD data might be misleading sometimes due to different statistical sampling and interferences from sidewall roughness. In this work we explore the capability of CD-AFM as an accurate in-line CD reference metrology. Being a member of scanning profiling metrology, CD-AFM has the advantages of avoiding e-beam damage and minimum sample damage induced CD changes, in addition to the capability of more statistical sampling than typical cross section metrologies. While AFM has already gained its reputation on the accuracy of depth measurement, not much data was reported on the accuracy of CD-AFM for CD measurement. Our main focus here is to prove the accuracy of CD-AFM and show its measuring capability for semiconductor related materials and patterns. In addition to the typical precision check, we spent an intensive effort on examining the bias performance of this CD metrology, which is defined as the difference between CD-AFM data and the best-known CD value of the prepared samples. We first examine line edge roughness (LER) behavior for line patterns of various materials, including polysilicon, photoresist, and a porous low k material. Based on the LER characteristics of each patterning, a method is proposed to reduce its influence on CD measurement. Application of our method to a VLSI nanoCD standard is then performed, and agreement of less than 1nm bias is achieved between the CD-AFM data and the standards value. With very careful sample preparations and TEM tool calibration, we also obtained excellent correlation between CD-AFM and TEM for poly-CDs ranging from 70nm to 400nm. CD measurements of poly ADI and low k trenches are also reported, and both show good correlation to in-line CD-SEM results.

Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations

This paper investigated various approaches to integrate Cu and extra low-k dielectric (ELK, k=2.5~2.2) for dual damascene fabrication. We demonstrate a trench-first hard mask process flow without k degradation by ash-free process and a novel pore sealing technique. In addition, we have extended this pore sealing concept to a via-first PR mask approach for porous ELK of 2.2. Both optimized hard mask and PR mask process flows are demonstrated promising for Cu/ELK integration for 65/45/32nm generations

Direct Non-Contact Electrical Measurement of Low-k Damage in Patterned Low-k Films by a Near-Field Scanned Microwave Probe

We demonstrate a near-field scanned microwave probe and specific test keys for direct non-contact electrical measurement of low-k dielectric constant and damage after deposition, during trench/via processing, and after metallization. This work successfully defines the dielectric constant and the thickness of the damaged layer in patterned low-k films, and is the first demonstration of a metrology for electrical in-line measurements of low-k damage. Furthermore, we point out the integration issue of porous low-k by using this novel technique

Application of optical CD metrology based on both spectroscopic ellipsometry and scatterometry for Si-recess monitor

Scatterometry is gaining popularity in recent years as it shows itself as a worthy contender among existing metrology systems. Scatterometry provides fast, accurate and precise profile information, which is valuable for in-line process control in production environment. Scatterometry applications widely adopted in IC fabs include poly gate ADI and AEI, and shallow trench isolation depth measurements. Recently, the mobility enhancement by compressive strain at source/drain is reported which improves greatly PMOS Idsat. In this work, we extend the application domain of scatterometry technology to two-dimensional recessed Si profile used in strained source and drain (SSD) structures. Complexity of SSD structures measurement by scatterometry requires the use of many parameters in modeling, which hinders a stable library setup. Our approach in circumventing this issue is to identify the most sensitive parameters first and then further reduce the number of variables through an effective medium approximation (EMA). This paper will discuss the preparation, experiments, and results of the scatterometry measurements. The extracted data have been compared with transmission electron microscopy results. Good correlation in depth and profile are observed. In addition, we have performed repeatability test and fault detection checks and the trend chart indicates that our methodology is very robust for in-line process monitor.