Fareen Adeni Khaja

Physical understanding of cryogenic implant benefits for electrical junction stability

We investigate the effect of cryogenic temperature implants on electrical junction stability for ultra shallow junction applications for sub-32 nm technology nodes and beyond. A comprehensive study was conducted to gain physical understanding of the impact of cryogenic temperature implants on dopant-defect interactions. Carborane (C2B10H12) molecule, a potential alternative to monomer boron was implanted in carbon preamorphized silicon substrates at cryogenic implant temperatures. Results indicate implants at cryogenic temperatures increase dopant activation with reduced diffusion, resulting in lower sheet resistance for a lower junction depth. Further, this study emphasizes the benefits of co-implants performed at cryogenic temperatures as alternative to traditional preamorphizing implants.

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation

Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρ_c) of ~2×10^-9 Ω·cm² on Si_0.3Ge_0.7:B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρ_c on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P. A simple Ti based CMOS contact flow is thus proposed. Several B doping and activation methods on SiGe:B are also compared in this work.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

Bulk FinFET junction isolation by heavy species and thermal implants

One of the challenges for bulk-Si FinFET is forming the junction isolation at the 14nm node and beyond. As the fins are scaled, source-drain punch-through can occur, which causes large leakage currents. A punch-through stop (PTS) layer/structure at the bottom of the fin is introduced to suppress this sub-fin leakage current. However, the introduction of PTS may result in dopant back diffusion into the active fin region from the PTS implant(s). This may result in device shift and variability. In this paper, we investigated novel approaches to reduce dopant back diffusion into the active fin region. Specifically, we studied the impact of (1) Carbon co-implants to block the dopant up-diffusion into the active fin region, (2) implants with heavy species at room temperature, and (3) thermal implants with heavy species. Results show that a lower channel concentration is achieved with antimony. These approaches can be extended to develop junction isolation for bulk FinFETs for 10nm and beyond.

Two-terminal diode steering element for 3D X-bar memory

We review recent progress in the application of the two-terminal diode steering element for 3D crossbar (X-bar) memory. Such architecture is emerging as one of the strong candidates for non-volatile memory to enable mobile computing with high speed, low power, and low cost. We address process, integration, and device scaling requirements of the steering element for fabricating PCRAM and metal oxide ReRAM cells. We also discuss in detail integration of ion implantation and activation to achieve the 50nm tall diode pillar needed for sub-2xnm 3D X-Bar memory.

PMOS contact resistance solution compatible to CMOS integration for 7 nm node and beyond

We report a PMOS contact resistivity (pc) improvement strategy by forming Ge-rich contact interface which is compatible to Ti/Si(Ge) system and CMOS integration flow. Short pulsed (nsec) laser anneal and advanced treatment during pre-clean have shown to be effective to segregate Ge towards SiGe surface resulting in PMOS ρc improvement. With Ge% increasing from 45 to 100%, pc improved three-fold, from 1.2e-8 to 2.8e-9 Ωcm2, due to bandgap modulation and preferred Fermi-level pinning [1]. In the end, we propose a CMOS-integration-compatible contact flow which addresses ρc optimization for both PMOS and NMOS contact.

Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond

The continuing reduction of contact resistivity (ρC) is a critical challenge for device performance. In this paper the ρC reduction for n-SD (source/drain) is demonstrated using post-silicide implantation of Se or P into Ni(Pt) silicide, with various energies/doses and laser anneal conditions. The improvement of ρC is achieved without sacrificing junction integrity/leakage. Hence laser assisted post-silicide implantation can be a key enabler to realize low silicide contact for n-SD for the 14 nm node and beyond.

Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction

Nickel silicide (NiSi) contacts are adopted in advanced CMOS technology nodes as they demonstrate several benefits such as low resistivity, low Si consumption and formation temperature. But a disadvantage of NiSi contacts is that they exhibit high electron Schottky barrier height (SBH), which results in high contact resistance (Rc) and reduces the NMOS drive current. To reduce SBH for NMOS, we used phosphorous (P) ion implantation into NiPt silicide with optimized anneal in order to form dopant segregated Schottky (DSS). Electrical characterization was performed using test structures such as Transmission Line Model, Cross-Bridge Kelvin Resistor, Van der Pauw and diodes to extract Rc and understand the effects of P+ DSS on ΦBn tuning. Material characterization was performed using SIMS, SEM and TEM analysis. We report ∼45% reduction in Rc over reference sample by optimizing ion implantation and anneal conditions (spike RTA, milli-second laser anneals (DSA)).

Sub-10 −9 Ω·cm 2 contact resistivity on p-SiGe achieved by Ga doping and nanosecond laser activation

We report record breaking values for PMOS source drain (S/D) contact resistivity, ρ<inf>c</inf> < 10⁻⁹Ω·cm². These were obtained by shallow Ga ion implantation on Si<inf>0.4</inf>Ge<inf>0.6</inf> in combination with subsequent pulsed nanosecond laser anneal (NLA). Cross section transmission electron microscopy (XTEM) shows the pc reduction mechanism is based on Ga and Ge segregation towards the surface.

Ultra-low (1.2×10 −9 Ωcm 2 ) p-Si 0.55 Ge 0.45 contact resistivity (ρ c ) using nanosecond laser anneal for 7nm nodes and beyond

The recent FinFET scaling for 10–7nm node has resulted in significantly reduced contact areas for source/drain regions, leading to high contact resistance (Rc) [1-3]. Hence, it has become extremely critical to reduce the contact resistivity (ρ<inf>c</inf>) to < 1×10⁻⁹Ω.cm². ρ<inf>c</inf> can be reduced by increasing the dopant concentration at the metal/semiconductor interface and by lowering the barrier height [4]. Several studies have reported improvements in NMOS ρ<inf>c</inf> for Ti-based contacts using highly doped Si:P epi and advanced implant and activation techniques [5, 6]. For TiSi<inf>2</inf> based contacts, the Schottky barrier height (SBH) for n-ype silicon is low; however, it is slightly higher for p type SiGe. Thus, there is a strong requirement to improve the PMOS ρ<inf>c</inf> when Ti based contacts are used for both NMOS and PMOS.