Benoit Lasbouygues

Temperature- and Voltage-Aware Timing Analysis

In the nanometer era, the physical verification of a CMOS digital circuit becomes a long, tedious, and complex task. Designers must indeed account for numerous new factors that impose a drastic change in validation and physical-verification methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static-timing engines. However, the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on nonlinear-derating coefficients, to account for these environmental variations. Based on temperature- and voltage-drop computer-aided-design tool reports, this method allows computing the propagation delay of logical paths considering the operating conditions of each cell. As the statistical timing analysis does, the proposed approach reduces design margins compared to worst/best case corner analysis with fixed voltage and temperature values, a gain of 10% on the delay has been observed for critical paths

Logical effort model extension to propagation delay representation

The logical effort method is widely recognized as a pedagogical way allowing designers to quickly estimate and optimize single paths by modeling equivalently propagation delay and transition time. However, this method necessitates a calibration of all the gates of the library and appears suboptimal in real combinatorial paths for satisfying tight timing constraints. This is due to the inability of the logical effort model in capturing I/O coupling and input ramp effects that distinguish the transition time from the propagation delay. Using an analytical modeling of the supply current that flows in simple gates during their switching process, this paper introduces an extension of the logical effort model that considers the I/O coupling capacitance and the input ramp effect. Validation of this model is performed on 130-nm STMicroelectronics technology. A compact representation of CMOS library timing performance is given as a possible application of the proposed model. The choice of sampling points to be used in look-up tables as representative steps of the design range is also discussed

Timing analysis in presence of supply voltage and temperature variations

In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of numerous new factors that impose a drastic change in validation and physical verification methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering the operating conditions of each cell.

Temperature and voltage aware timing analysis: application to voltage drops

In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of new factors that impose a significant change in validation methods. One of these major changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the delay of logical paths considering more realistic operating conditions for each cell. Application is given to the analysis of voltage drop effects on timings

Temperature dependence in low power CMOS UDSM process

In low power UDSM process the combined use of reduced value of the supply voltage and high threshold voltage value may greatly modify the temperature sensitivity of designs, which becomes structure and transition edge dependent. In this paper we propose a model for determining the temperature coefficient of CMOS structures and defining the worst Process, Voltage and Temperature condition to be verified for qualifying a design. This model is validated on two 0.13μm processes by comparing the calculated values of the temperature coefficient of the performance parameters to values deduced from electrical simulations (Eldo). Application to combinatorial path gives evidence of the occurrence of temperature inversion that is structure and control condition dependent and must carefully be considered for robust design validation.

Temperature dependency in UDSM process

In low power UDSM process the use of reduced supply voltage with high threshold voltages may reverse the temperature dependence of designs. In this paper we propose a model to define the true worst Process, Voltage and Temperature conditions to be used to verify a design. This model will provide an accurate worst case definition for high performance designs where standard design margins are not applicable. This model is validated at either cell level or path level on two different 130nm process.

Physical Extension of the Logical Effort Model

The logical effort method has appeared very convenient for fast estimation and optimization of single paths. However it necessitates a calibration of all the gates of the library and appears to be sub-optimal for a complex implementation. This is due to the inability of this model in capturing I/O coupling and input ramp effects. In this paper, we introduce a physically based extension of the logical effort model, considering I/O coupling capacitance and input ramp effects. This extension of the logical effort model is deduced from an analysis of the supply gate switching process. Validation of this model is performed on 0.18μm and 0.13μm STM technologies. Application is given to the definition of a compact representation of CMOS library timing performance.