Bernhard Fiegl

Manufacturing self-aligned polysilicon fet devices isolated with maskless shallow trench isolation and gate conductor fill technology with active devices and dummy doped regions formed in mesas

Method of filling shallow trenches

Methods for protecting device components from chemical mechanical polish induced defects

Method of manufacturing FET devices with maskless shallow trench isolation (STI)

Methode zum Schutz von Anordnungen gegen durch chemisch-mechanisches Polieren verursachte Fehler Method for protecting arrangements against diseases caused by chemical-mechanical polishing error

A process for the preparation of FET devices with flat, maskless grave Isolation

Method of protecting arrangements against diseases caused by chemical mechanical polishing errors

Method of preventing damage to substrate disposed under pad nitride layer of cmp induced mesa, and manufacture of shallow trench insulating field-effect transistor

Verfahren zur Herstellung von FET-Bauelementen mit flacher,maskenloser Grabenisolation Process for the preparation of FET devices with flat, maskless grave isolation

Verfahren zur Herstellung von FET-Bauelementen mit flacher,maskenloser Grabenisolation