Bernhard Rebhan

Cu-Cu wafer bonding: An enabling technology for three-dimensional integration

Wafer-level hybrid bonding with Cu/SiO2 is a very promising technique to fabricate three-dimensional integrated circuits, because it enables high performance operation with low power consumption as well as low 3D stacking costs. For a successful hybrid bonding process, the particular bonding properties of unstructured Cu-Cu and Si-SiO2 wafer bonding were investigated. For Cu-Cu bonding, the Cu oxide removal prior to bonding is one of the keys to success. The combination of ex-situ citric acid and in-situ forming gas pre-treatments before bonding resulted in sufficient bonding quality at low temperature as low as 200°C. In the case of plasma activated Si-direct wafer bonding, a bonding strength similar to the Si bulk fracture strength was achieved. So far, the isolated Si-direct and Cu-Cu thermo-compression wafer bonding processes were successfully demonstrated. Finally, crucial interdependencies, such as the plasma activation on Cu surfaces and the citric acid treatment on Si surfaces, for a successfully hybrid wafer bonding were presented.

Cu-SiO2 hybrid bonding simulation including surface roughness and viscoplastic material modeling: A critical comparison of 2D and 3D modeling approach

Abstract Cu-SiO2 direct hybrid bonding is considered as one of the key enabling technologies for 3D integration. Previous studies showed that the main process parameters influencing the bonding quality are temperature and annealing time, as well as the mechanical stress at the Cu-Cu interface. The latter is influenced by thermo-mechanical stress introduced by the coefficient of thermal expansion mismatch of SiO2 and Cu and by geometrical effects. The modeling approach of the present study aims to shed light on the influence of surface roughness on the contact area formation between Cu pads. Roughness profiles measured with atomic-force microscopy are directly used as input for the simulation. This introduces considerable computational effort when explicitly modeled within finite element simulation. A sub-modeling technique is used to reduce the numerical cost. The common 2D modeling approach is critically compared to full 3D modeling of the surface topography. The dominant micro-mechanical temperature dependent deformation mechanisms are taken into account by continuum mechanics material models from literature. Accordingly, the stress driven instantaneous dislocation glide and the diffusion triggered climb assisted dislocation glide are taken into account by corresponding plasticity and creep material models.

3D integration by wafer-level aligned wafer bonding

Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.

Low temperature wafer bonding for wafer-level 3D integration

This work presents new results on low temperature wafer bonding processes. Low temperature Cu-Cu thermo-compression bonding was successfully performed at process temperatures lower than 200°C. A process flow was developed for stacking thin Si wafers (<;25 μm) using a combination of temporary bonding with rigid carrier and plasma activated wafer bonding. Together with high accuracy optical alignment technology the two processes can be used to address the needs of manufacturing processes based on TSV technology.

Metal wafer bonding for 3D interconnects and advanced packaging

Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in manufacturing processes.

Copper-oxide reduction for low-temperature wafer bonding

Silicon wafers with a 500 nm sputtered Cu layer were successfully bonded at low temperatures of 175°C for 30 min in forming gas. Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) were used for oxide detection and microstructure imaging.