Thomas Wagenleitner

<200 nm Wafer-to-wafer overlay accuracy in wafer level Cu/SiO2 hybrid bonding for BSI CIS

Sub 200 nm wafer-to-wafer (w2w) overlay accuracy on the entire 300 mm wafer was successfully demonstrated via wafer level Cu/SiO2 hybrid bonding. Cu bonding pads relevant for back-side illuminated (BSI) complementary metal oxide semiconductor (CMOS) image sensor (CIS) were used for the experiment. Further, a crucial component to improve the overlay accuracy, namely the overlay model which identifies systematic alignment errors, was described.

Monolithic IC integration key alignment aspects for high process yield

Lithographic scaling has been the main growth driver to follow Moores law of cost reduction and performance increase for several decades. However, the 22nm node appears to be a game changer, where other core processes besides lithography have to be taken into account. Monolithic integration is one solution, where lithographic scaling is replaced by integration in vertical direction. Stacking and electrically contacting several semiconductor layers is challenging, as multiple unit processes have to be solved and put together. One of the key processes for monolithic integration is aligned wafer-to-wafer bonding. Besides optimization of the alignment accuracy, particle cleaning or plasma activation, earlier processing steps have important influence to a high yield processing of monolithic integrated circuits.

Influencing factors in high precision fusion wafer bonding for monolithic integration

Both fusion and hybrid wafer bonding are enabling increasing integration density as well as advanced device integration strategies. In any case, wafer-to-wafer overlay accuracy is the most critical factor for successful integration in 3D stacked devices. Despite alignment of both wafers is of major impact for the post-bond overlay accuracy, initiation and control of the bond wave between both substrate wafers the essential. During contacting device wafer surfaces, wafer stress as well as bow is influencing the bond wave dynamics. Engineering the continuous wave dynamics and influencing parameters are both key for optimum post-bond overlay accuracy. Any wafer stress will result into distortion of patterns and additional misalignment term. Despite typical distortion values are well below 50nm already, further optimization of both wafer bonding as well as wafer preparation and preprocessing are key for hybrid and monolithic integration.

Wafer bonding for CMOS integration and packaging

The use of CMOS wafers imposes important limitations for W2W (Wafer-to-Wafer) or C2W (Chip-to-Wafer) bonding: low processing temperature (max. 400°C), no mobile ions and extreme cleanliness. Additional to substrates preparation a special focus is directed on cleaning and maintaining the wafers clean during processing. Special cleaning processes were adopted for CMOS-compatible applications. The main challenges raised by CMOS-compatible wafer bonding in terms of processing and process control were identified and process solutions will be presented illustrated with examples.

CMOS-compatible aligned fusion wafer bonding

Wafer bonding is a very attractive technology for applications in wafer-level 3D integration. However, most of the bonding processes are not compatible with CMOS technology in terms of process temperature and contamination levels. A low temperature fusion bonding process is presented as an example of how the wafer bonding issues were successfully solved and applied to manufacturing processes.

3D-SoC integration utilizing high accuracy wafer level bonding

This paper describes ultra-fine pitch 3D integration development using wafer level Cu/insulator hybrid bonding approach on 300mm substrate. Via-middle process with TSV dimension of 5×50μm is utilized to demonstrate and characterize vertical interconnects formed via face-to-face wafer-to-wafer (W2W) bonding. Key process steps are introduced with specific requirements and challenges. A non-SiO2 insulator is studied and chosen to enable a high mechanical bond strength with a low temperature anneal (≤250 °C). High alignment accuracy (< 400nm) is achieved with an advanced bonding system, which allows comprehensive characterizations of interconnect pitch scaling through various test structures. Finally, a high repeatability of the electrical performance of 3.6 μm pitch bonded structures is demonstrated statistically across numerous wafer pairs thanks to the precise Cu-Cu contacts established during bonding.

Metal wafer bonding for 3D interconnects and advanced packaging

Metal films can be used as bonding layers at wafer-level in manufacturing processes for device assembly as well as just for electrical integration of different components. One has to distinguish between two categories of processes: metal thermo-compression bonding on one side, and bonding with formation of a eutectic or an intermetallic alloy layer. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with special emphasis on vacuum packaging) metal wafer bonding is a very important technology in manufacturing processes.