Thomas Plach

Cu-Cu wafer bonding: An enabling technology for three-dimensional integration

Wafer-level hybrid bonding with Cu/SiO2 is a very promising technique to fabricate three-dimensional integrated circuits, because it enables high performance operation with low power consumption as well as low 3D stacking costs. For a successful hybrid bonding process, the particular bonding properties of unstructured Cu-Cu and Si-SiO2 wafer bonding were investigated. For Cu-Cu bonding, the Cu oxide removal prior to bonding is one of the keys to success. The combination of ex-situ citric acid and in-situ forming gas pre-treatments before bonding resulted in sufficient bonding quality at low temperature as low as 200°C. In the case of plasma activated Si-direct wafer bonding, a bonding strength similar to the Si bulk fracture strength was achieved. So far, the isolated Si-direct and Cu-Cu thermo-compression wafer bonding processes were successfully demonstrated. Finally, crucial interdependencies, such as the plasma activation on Cu surfaces and the citric acid treatment on Si surfaces, for a successfully hybrid wafer bonding were presented.

Plasma Activation for Low Temperature Wafer Bonding

Despite the existence of well established wafer bonding processes within this temperature range, there is a high interest in developing low temperature direct (fusion) bonding processes. The choice of a direct bonding process is in some cases motivated by facts as contamination concerns (e.g. Na contamination during an anodic bonding process), CMOS compatibility (no Au, Sn), or the need to simplify the process flow for increased manufacturing efficiency (no additional processes required for bonding layers definition).

Influencing factors in high precision fusion wafer bonding for monolithic integration

Both fusion and hybrid wafer bonding are enabling increasing integration density as well as advanced device integration strategies. In any case, wafer-to-wafer overlay accuracy is the most critical factor for successful integration in 3D stacked devices. Despite alignment of both wafers is of major impact for the post-bond overlay accuracy, initiation and control of the bond wave between both substrate wafers the essential. During contacting device wafer surfaces, wafer stress as well as bow is influencing the bond wave dynamics. Engineering the continuous wave dynamics and influencing parameters are both key for optimum post-bond overlay accuracy. Any wafer stress will result into distortion of patterns and additional misalignment term. Despite typical distortion values are well below 50nm already, further optimization of both wafer bonding as well as wafer preparation and preprocessing are key for hybrid and monolithic integration.

Key enabling processes for more-than-moore technologies

The continuation of Moores law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Than Moore” with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into high-volume manufacturing (HVM) putting “More Than Moore” in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques - low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.