Jürgen Burggraf

Integration of a temporary carrier in a TSV process flow

Three-dimensional (3-D) wafer stacking technologies offer new possibilities in terms of device architecture and miniaturization [1–3]. To stack wafers, reliable through-silicon vias (TSVs) and interconnections must be processed into ultrathin wafers, and such processing is made possible by new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives can offer a variety of properties sufficient for withstanding the TSV processes: flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning processes. This paper demonstrates that, contrary to tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive meets all the requirements named above for reliable TSV processing on 8-inch active wafers. We will first describe formation of TSVs with aspect ratios of 1:1 and 2:1 into thinned wafers.

Facilitating Ultrathin Wafer Handling for TSV Processing

Making reliable through-die interconnects for three-dimensional (3-D) wafer stacking technologies requires a reduction in wafer thickness combined with a larger wafer diameter, which in turn requires new methods for wafer handling. Of the different wafer-level bonding techniques, temporary wafer bonding adhesives are becoming increasingly important in both integrated circuit and MEMS technologies. This new generation of adhesives must possess a variety of properties to be integrated into all the required processes, including adequate flow properties, mechanical strength, thermal stability, chemical resistance, and easy debonding and cleaning. The purpose of this paper is to demonstrate that, contrary to the tapes and waxes currently used for temporary bonding, a new removable high-temperature adhesive* meets all the requirements named above for reliable through-silicon via (TSV) processing on 8-inch wafers. After a presentation of the typical temporary wafer bonding process flow, the article will describe the development and the properties of the material. Secondly it will present the TSVs formed in a 70-mum thinned silicon wafer using the temporary bonding process.

Edge Protection of Temporarily Bonded Wafers during Backgrinding

Edge chipping during backgrinding is one of the main challenges of processing temporarily bonded wafers. The edge chipping may propagate during subsequent process steps and eventually result in yield loss. We conducted a study to compare different methodologies for wafer edge protection during backgrinding, including using pre-thinned carrier wafers, large carrier wafers, edge-trimmed device wafers, and material edge modification. This paper will introduce the metrology developed to quantify edge chipping and compare the results from different protection methods.

Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bonding

We report recent advances in tool and process hardening of a first of its kind 300 mm wafer-to-wafer (WtW) preprocessing, aligning, and bonding integrated tool. We have demonstrated sub-500 nm post-bond alignment accuracies for 300 mm WtW face-to-face (FtF) Cu-Cu thermocompression bonds, WtW FtF Si-Si fusion bonds, and WtW FtF oxideoxide fusion bonds. All process of record (POR) recipes that were developed had undetectable voids based on scanning acoustic microscope (C-SAM) measurements on representative bonded Cu, oxide, and Si blanket wafers. Optimized bonded patterned wafer splits in the Cu-Cu WtW thermocompression bonding step have shown alignment accuracies down to ∼190 nm, the highest accuracy to date. Using an infrared-enabled, high speed focused ion beam (FIB) system (with XeF2) with a CAD overlay function to assist in selective sample preparation, we have verified that the bonding interfaces at the via chain structures with 1–5 μm diameter vias show no interfacial voids. Also, there is evidence of Cu interdiffusion, as supported by transmission electron microscopy (TEM) and electron backscattering diffraction (EBSD) data.

Thin wafer handling and processing-results achieved and upcoming tasks in the field of 3D and TSV

As microelectronic applications and technologies are getting more demanding, it is being demonstrated that the 3rd (vertical) dimension on wafer-processing technology is enabling applications and products with higher performance. Approaching the 3rd dimension in wafers is actually considered and realized through emerging TSV (through silicon via) technology and thinned wafers at the same time. Thin (<100 ¿m) silicon wafers which are commonly used for TSV formation exhibit increased instability and fragility. The lack of mechanical stability and the increased fragility present a major challenge to maintain high yield levels in volume manufacturing environments. The most accepted handling solution for UltraThin® wafers is the use of temporary bonding and debonding techniques utilizing a rigid carrier wafer to provide sufficient mechanical support. Once the product wafer is temporarily bonded to the carrier wafer, it is ready for backside processing including back-thinning, through-silicon via (TSV) formation, etc. The product wafers can be pre-processed wafers with CMOS devices as well as e.g. substrates with high-topographies like solder-balls. Additional stacking of ultra thin wafers or bonding chips to thin wafers are new requirements to be considered.

Thin wafer processing - yield enhancement through integrated metrology

Thin wafer handling and processing is performed by temporary bonding to a rigid carrier wafer. The rigid carrier wafer gives mechanical support during wafer thinning and backside processing. Finally the thin wafer is debonded from the carrier wafer and attached to a dicing tape on film frame. While this technology has been demonstrated for a couple of years now in pilot line and small volume, it is an entirely different story to transfer such a technology to high volume manufacturing (HVM).

Recent progress in thin wafer processing

The ability to process thin wafers with thicknesses of 20-50um on front- and backside is a key technology for 3D IC. The most obvious reason for thin wafers is the reduced form factor, which is especially important for handheld devices. However, probably even more important is that thinner wafers enable significant cost reduction for TSVs. The silicon real estate consumed by the TSVs has to be minimized in order that the final device provides a performance advantage compared to traditional 2D devices. The only way to reduce area consumption by the TSVs is to reduce their diameter. For a given wafer thickness the reduction of TSV diameter increases the TSV aspect ratio. Consensus has developed on the use of Temporary Bonding / Debonding Technology as the solution of choice for reliably handling thin wafers through backside processing steps. While the majority of the device manufacturing steps on the front side of the wafer will be completed with the wafer still at full thickness, it will be temporarily mounted onto a carrier before thinning and processing of the features on its backside. Once the wafer reaches the temporary bonding step, it already represents a significant value, as it has already gone through numerous processing steps. For this reason, inspection of wafers prior to non-reworkable process steps is of great interest. Within the context of Temporary Bonding this consideration calls for inline metrology that allows for detection of excursions of the temporary bonding process in terms of adhesive thickness, thickness uniformity as well as bonding voids prior to thinning of the product wafer. This paper introduces a novel metrology solution capable of detecting all quality relevant parameters of temporarily bonded stacks in a single measurement cycle using an Infrared (IR) based measurement principle. Thanks to the IR based measurement principle, the metrology solution is compatible with both silicon and glass carriers. The system design has been developed with the inline metrology task in mind. This has led to a unique system design concept that enables scanning of wafers at a throughput rate sufficient to enable 100% inspection of all bonded wafers inline in the Temporary Bonding system. Both, current generation temporary bonding system throughputs and future high volume production system throughputs as required by the industry for cost effective manufacturing of 3D stacked devices were taken into account as basic specifications for the newly developed metrology solution. Sophisticated software algorithms allow for making pass/ fail decisions for the bonded stacks and triggering further inspection, processing and / or rework. Actual metrology results achieved with this novel system will be presented and discussed. In terms of adhesive total thickness variation (TTV) of bonded wafers, currently achieved performance values for postbond TTV will be reviewed in light of roadmaps as required by high volume production customers.

Effect of Process Variables on Glass Frit Wafer Bonding in MEMS Wafer Level Packaging

Among different MEMS wafer level bonding processes glass frit bonding provides reliable vacuum tight seals in volume production. The quality of the seal is a function of both seal glass materials and the processing parameters used in glass frit bonding. Therefore, in this study Taguchi L18 screening Design of Experiment (DOE) was used to study the effect of materials and process variables on the quality of the glass seal in 6” silicon wafers bonded in EVG520IS bonder. Six bonding process variables at three levels and two types of sealing glass pastes were considered. The seals were characterized by Scanning Acoustic Microscopy (SAM), cross sectional Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Analysis (EDAX). The results were quantified into four responses for DOE analysis. Key results are a) peak temperature has the strongest influence on seal properties, b) hot melt paste has significantly lower defects compared to liquid paste, and c) peak firing temperatures can be as low as 400°C under certain conditions.

Thin WLFO and based WLSiP enabling WL3D, realized using Temporary Reconstituted Panel Bonding Technology

The interest in FOWLP as new flexible packaging technology platform is continuously increasing. High volume capability is proven for configurations with single die (WLFO), multi-die side-by-side, partially with discrete passives integration (WLMCM and WLSiP), both with single sided single and multiple RDL layers. The next step to achieve higher integration density, e.g. for mobile and IoT applications, is to go in the third dimension (WL3D/WLPoP) with total package thickness below 1mm, targeting 0.8mm and even less in the next development step. High design flexibility, superior performance and small form-factor in x and y, but even more important in z-dimension, are the essential packaging characteristics required for this type of smart system integration. The eWLB based WLFO technology platform of NANIUM promises to deliver all of those requirements. While previous generations of WLFO packages only consisted of one plane of single or multiple RDL layers (frontside RDL at BGA side), recent evolutions enab...

3D integration by wafer-level aligned wafer bonding

Wafer bonding is an attractive technology enabling manufacturing of complex wafer-level 3D architectures. The continuous demand for device size shrinking and performance improvement pushed for the development of new manufacturing technologies. This work reviews the main challenging raised for the wafer bonding processes and presents new developments in the aligned wafer bonding processes.