Sandeep B. Sane
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Featured researches published by Sandeep B. Sane.
semiconductor thermal measurement and management symposium | 2005
Unnikrishnan Vadakkan; Gregory M. Chrysler; Sandeep B. Sane
A numerical study is performed to characterize the thermal and mechanical performances of silicon/water vapor chambers as heat spreaders for electronics cooling applications and to compare their performance against Cu heat spreaders. 2D flow and energy equations are solved in the vapor and liquid regions, along with conduction in the wall. An equilibrium model for heat transfer and a Brinkman-Forchheimer extended Darcy model for fluid flow are solved in the wick region. In addition to thermal modeling, FEA is also performed to study the impact of the proposed design on die stresses. The study shows that this system can match or thermally perform better than a more standard Cu spreader while also reducing the compressive stress in the Si by as much as 96%. Analysis shows that there are two main factors contributing towards the reduction of stress in the Si die, namely, the better CTE match between the Si die and the Si heat spreader and higher compliance (less stiffness) of the vapor chamber compared to standard heat spreaders. Thus Si vapor chambers provide a good design alternative to a standard Cu heat spreader without compromising on the reliability and performance of the Si.
ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference | 2005
Sandeep B. Sane; Shalabh Tandon; Biju Chandran; Tsgereda Alazar; Leonard R. Sorenson
Integrating a low-K ILD layer within silicon is key to reducing RC delays. However, low-K ILD materials typically have low mechanical strength, making their incorporation with lead free interconnects an industry-wide challenge. It is well known that conversion to lead free first level interconnects increases die backend stresses due to the higher melting temperature and increased solder stiffness. The paper will focus on the measurement of the effective silicon backend strength after subjecting the dice to different fabrication and assembly steps. The effective strength will also be evaluated post reliability stress exposure to eventually understand the life of these films. The paper will describe how a commercially available Dage 4000 tool was modified for this application. Bump pull was carried out using a 100μm tweezers, while bump shear used 1mil (25.4μm) wide stylus. Static and dynamic calibration was first carried out to ensure repeatability and reproducibility of the results. Peak force and failure modes were used as metrics to compare the effectiveness of different experimental legs. Traditional failure analysis approach of mechanical polishing, or when needed, use of FIB for sample preparation, with subsequent SEM/EDX analysis was utilized to understand the failure mechanism. Data suggests that shear and pull lead to different failure modes. Bump shear mainly led to failure at the bump/polyimide interface and did not necessarily correspond to the weakest layer or interface in the silicon backend. Whereas bump-pull, which applies tensile force to the stack up, lead to failures in the weakest layer, typically the low-K ILD, in the silicon backend. Hence, bump pull provided the advantage over shear as it allowed evaluation of the weakest interface in the stack up. Two case studies are discussed to demonstrate on how bump pull/shear metrologies were used to understand the impact of different assembly/FAB process variables and highly accelerated steam test (HAST) reliability stress on silicon backend strength. First case study shows influence of assembly flux on silicon backend strength, while second case study describes impact of HAST on different FAB backend processes.Copyright
electronic components and technology conference | 2008
Tieyu Zheng; Min Tao; Patrick Nardi; Mitul Modi; Sandeep B. Sane; Ibrahim Bekar
Organic substrates in electronic packaging are made of laminated dielectric and plated copper layers surrounding a fiber-reinforced glass core. Their constituent materials have typically been assumed to be linear elastic for simplicity in the microelectronic packaging analysis. However, the viscoelasticity of dielectric materials and the viscoplasticity of copper in the substrates impact the substrate behavior and in some cases must be considered. This paper presents a series of investigations on the non-linear time-dependent behavior of organic packages through experimentation and finite element analysis (FEA), including characterization and model validation of substrate core, modeling simplification and case study of packages during the package assembly process, and package substrate behavior in the system stack.
ASME 2005 Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems collocated with the ASME 2005 Heat Transfer Summer Conference | 2005
Shankar Ganapathysubramanian; Sandeep B. Sane; Richard Raymond Dimagiba; Biju Chandran
Viscoelastic analysis for numerical modeling of IC assembly processes are generally non-linear and require extensive time and computational resources when compared to a linear elastic analysis. Experimental identification/approximation of the viscoelastic properties (in terms of the Prony series) of any polymeric material is also an exhaustive effort. These drawbacks in experimental procedures and modeling activities have forced us to explore the possibility of approximating viscoelastic response of a polymer with an appropriate linear-elastic model. This paper discusses the impact of different approximation methodologies for a viscoelastic material most commonly used in electronic packaging — the underfill material in flip-chip technology. The modeling methodologies discussed here include the use of long term modulus, short term modulus and other “effective” stiffness measures to approximate the response of underfills during assembly processes. The package response, from each of these models, has been compared to the package response from a linear viscoelastic analysis assuming underfill materials to behave as Maxwell solids. It has been observed that the short term modulus consistently over predicts the ILD (interlayer dielectric in the silicon backend) peel stress for various underfill materials. In addition, the paper also explores the existence of an “effective” stiffness that can be used in lieu of a full fledged viscoelastic analysis. The ability to estimate this “effective” stiffness using available temperature dependent modulus data (from DMA tests) is also discussed. The applicability of this effective metric to different underfill materials has also been explored. In conclusion, this study highlights the need for accurate characterization of polymeric materials so that numerical predictions can provide realistic risk assessments for future packaging technologies.Copyright
Archive | 2008
Ravi Mahajan; Sandeep B. Sane
Archive | 2007
Sandeep B. Sane; Nachiket R. Raravikar
Archive | 2006
Shankar Ganapathysubramanian; Sandeep B. Sane
Archive | 2005
Sandeep B. Sane; Biju Chandran
Archive | 2009
Sandeep B. Sane; Biju Chandran
Archive | 2005
Sandeep B. Sane; Nitin Deshpande; Chia-Pin Chiu