Boo Yang Jung

Process development of 10μm pitch Cu-Cu low temperature bonding for 3D IC stacking

A low temperature <;200°C Cu-Cu bonding process is developed for 3D IC stacking application. To prepare and activate good copper surface, three planarization processes and two surface treatment methods are studied in details and compared. Best surface treatment method is identified. It is found that good Cu-Cu direct bonding with high shear strength is achieved by the developed process and verified by the cross sectional structure. Low temperature Cu-Cu bonding for 3D IC applications is demonstrated by a high density Cu bump array structure with 10 μm pitch and 5 μm diameter. Chip-to-chip bonding approach is used for 3D IC stack bonding. Final cross sectional and daisy chain electrical measurement showed good connectivity of micro bump joints.

Package-level thermal management of a 3D embedded wafer level package

As the embedded wafer-level packaging (eWLP) technology evolves to capitalize on package-on-package (POP) technology, thermal analysis has been performed to investigate and improve the heat dissipation capability of the 3D package structure. 3D simulation models have been built to study the impact of the thermal properties (underfill material, passivation layer and mold compound) and geometries (over mold, passivation layer and Cu layer in RDL) on the package thermal performance. We also analyzed the thermal effect of the Cu percentage in each RDL layer. The top heat spreader, thermal via arry, bottom heat dissipation plate and two types of top thermal cases have employed to enhance the heat dissipation capability. In baseline conditions, without any enhancement structure, the 85°C temperature limit can be met, at a max total PoP power dissipation of 2W (Logic: 1.5W, memory: 0.5W). In the mobile device scenario, passive cooling solutions have been applied to the PoP structure, and a total power of 4W can be accommodated with the proposed cooling structures.

Heat Dissipation Capability of a Package-on-Package Embedded Wafer-Level Package

In this work, the thermal analysis is performed to investigate and improve the heat dissipation capability of the fan-out eWLP POP structure. The simulation scheme was validated with the available experimental results conducted previously by Hoe et al. [9]. The 3-D package studied is shown in Figure 1. The thermal performance of the initial POP structure is evaluated as the baseline case. Then, the impact of the internal factors (thermal properties and geometries) on heat dissipation capability of the 3-D packages is investigated and compared. In the mobile device scenario, passive cooling solutions are explored for heat removal improvement. The topside thermal cap provides additional thermal paths between the top and bottom packages, and achieves pronounced temperature decrease. The package lid of larger size and direct thermal path to PCB has enhanced the heat spreading capability, and achieved effective heat conduction from both top and bottom packages to the outside environment. A total heating power of 4 W in the POP can be dissipated, while maintaining the maximum die temperature under the operation limit (85 °C).

Development of low profile fan out PoP solution with embedded passive

Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high performance memory in mobile application. This PoP has an advantage of a smaller package size with high functionality due to stacking of two different packages. However a conventional PoP with PCB substrate has a limitation to meet the recent requirement of a low profile with high performance in the thin mobile application. A fan out wafer level packaging is one of promising solution to meet a low profile with high performance. The direct solder attach on the RDL layer in the wafer level package provide a low profile package and RDL formation beyond Si die area provide a high performance with allowing higher solder ball counts. Also an embedded passive into fan out wafer level package is able to provide the better performance as well as flexibility to extend to SiP (System in Package). In this study, a low profile fan out Package on Package was successfully demonstrated with 14.0×14.0mm of a bottom package and 8.0×8.0mm of top package as well as embedded passives. The top and bottom package were electrically connected through TMV (Through Mold Via) with electro-less plating. TMV (Through Mold Via) was characterized with various EMC materials such as filler size, contents and resin material. The optimization of passive component location in term of process and reliability was performed using mold flow simulation. Also an assembly process was developed to minimize the package warpage using thermo-mechanical simulation.

Thermo-mechanical reliability study on Package on Package (PoP) with Embedded Wafer Level Package (eWLP)

In order to improve the reliability of the proposed test vehicle of the Package on Package (PoP) with Embedded Wafer Level Package (eWLP) using through mold via (TMV) as vertical interconnect. In this paper, the solder joint reliability of eWLP PoP package was studied by the thermo-mechanical finite element simulation under the -40 °C to 125 °C thermal cycle loading conditions. The simulation results show that the critical solder ball is located at the diagonal corner solder ball of the bottom package. The effects of the structural parameters were indentified. The results show that the solder joint reliability can be enhanced by increasing the diameter and standoff of the solder ball, and reducing the overmold thickness of bottom package. Only using appropriate underfill and corner adhesive can enhance the reliability of solder ball. The underfill and corner adhesive material which are benefit to the solder ball reliability under thermal cycle loading were indentified and selected by the simulation.

Reliability study on through mold via (TMV) for 3D microelectronic packaging under thermal and moisture loadings

Through mold via (TMV) provides a potential solution for the 3D microelectronic packaging. The reliability of the TMV is one of the major concerns during its applications. In this paper, the reliability of the TMV structure used for the embedded wafer level packaging (eWLP) was studied by the finite element simulation under the moisture 85°C/85RH, reflow and thermal cycling loading conditions. Fracture mechanics was used to calculate the strain energy release rate of the delamination between the plating copper and molding compound. The effects of the material properties and structure parameters were examined by the simulation results. The efforts can provide some guidelines for the reliability design of the 3D microelectronic packaging with TMVs.

MEMS WLCSP development using vertical interconnection

As the demand of MEMS device in mobile application is increased, MEMS device packaging technology is facing to the challenge to reduce the size and thickness. One of promising packaging solution to overcome this challenge is WLCSP (Wafer Level Chip Scale Package) using TSV(Through Silicon Via)[1,2,3]. A WLCSP using TSV technology is able to provide the smaller form factor as this used a vertical interconnection through Si die instead of conventional wire bonding for interconnection between Si die and substrate. However TSV process is still limited to apply various products since it has higher process and material cost compare to conventional wire bonding package. This study proposes a novel cost effective MEMS WLCSP using Si pillar structure and Cu wire, which work as a vertical interconnection to reduce the package size and thickness. This structure is able to provide a lower cost than TSV process since separate expensive process such as DRIE and Cu filling, etc. is not required to form the vertical interconnection. As a bottom MEMS device, 2D — accelerometer device was used in this study, and cap wafer was bonded on bottom wafer using Al-Ge eutectic bonding with wafer to wafer bonding technology. In this study, different EMCs were evaluated to optimize the package structure in the view point of process such as warpage, void and EMC filling in the gap. Also parametric study of mechanical simulation is performed to predict the stress level of MEMS device with process flow and package thickness.

Simulation and testing for drop impact reliability of 3D eWLP

In this paper, the drop impact reliability of the 3D embedded wafer level package (eWLP) was studied by the experiment and finite element simulation. The drop impact reliability test of the 3D eWLP test vehicle was conducted under the loading of 1500 g within 0.5 ms. The failure mechanisms were identified through the failure analysis experiment. The experimental results show that the failure modes are the delamination at the interface between the dielectric layer and Cu pad and at the interface between the dielectric layer and die/epoxy molding compound (EMC) under the drop impact loading. The stress and strain behaviors of the solder ball and dielectric layer of the 3D eWLP were investigated by the finite element simulation. The simulation results show that the high level of peeling stresses happen to the dielectric layer under critical corner solder joint near the die edge and package edge of the bottom package which caused the delamination failures.

Development of compliant Cu pillar for flip chip package

A compliant flip chip bump design compromises of a polymer core inside a Cu pillar, a polymer encapsulated Cu pillar and the process flow to make such bumps for fine pitch flip chip package is proposed in this study. Both polymer core and polymer encapsulated Cu pillar structures are able to provide the compliance to the Cu pillar structure and reduce stress on low K dielectric layers. A structural analysis showed the polymer encapsulated bump and polymer core bump reduce the low K dielectric stress by 35% and 20%, respectively, compared to conventional Cu pillar structure. Also both compliant bump structures (polymer encapsulated and polymer core bump) increase solder joint thermal cycle life time by 55% and 30%, respectively.

Novel high performance millimeter-wave resonator and filter structures using embedded wafer level packaging (EWLP) technology

In this paper, a 60 GHz resonator is designed and implemented on embedded wafer level packaging (EWLP) platform. The resonator is constructed in substrate integrated waveguide (SIW) configuration with the molding compound as the filled in substrate material. Through molding vias (TMVs) are employed to realize the via fences and the top and bottom redistribution layers (RDLs) serve as the top and bottom metallic walls. The resonator exhibits a quality factor (Q-factor) of 88. The resonator is subsequently used to form a second-order bandpass filter by cascading two such resonators in a line. The insertion loss of the bandpass filter is smaller than 4.15 dB, and the return loss is larger than 12.95 dB. The fractional bandwidth is 3.5% at 59.20Hz.