Ding Mian Zhi

Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.

Process characterization of highly conductive silver paste die attach materials for thin die on QFN

In this paper, die attach process characterization on two type of highly conductive silver paste die attach materials was discussed. The first silver paste die attach materials (DA1) was used as a reference which is silver-loaded epoxy adhesive with high thermal conductivity of 60W/mK and electrical conductivity of 16Ms/m. Second silver paste die attach material (DA2) can be sintered with low pressure or pressure-less at temperature of 220°C to 280°C. DA2 material acquires high thermal conductivity range of 100–170W/mK and electrical conductivity range of 12–15Ms/m. Process specifications were set at die tilt < 1%, average bond line thickness between 25μm to 50μm and full die attach materials coverage without overflow of materials on top of dies surface. Process was optimized with 70μm thin silicon daisy chain chip with die size of 5mm×5mm on Ag plated QFN lead frame for both silver paste materials and achieved the required process specifications. Process optimized on DA1 achieved average bond line thickness ranged from 24.5μm to 30.5μm with die tilt less than 0.24% and DA2 had average bond line thickness ranged from 32.6μm to 44.2 μm with die tilt less than 0.15%. There was further evaluation on die attach process with silver sintered paste for different die thickness (which 50μm, 70μm and 175μm were used) on a fixed die size of 5mm×5mm. Porosity after die attach cure is always a curial factor which affects the modulus and conductivity of the device. Investigation on porosity of cured die attached materials was carrying out on different die size range from 0.5mm × 0.5mm to 5mm × 5mm. This helped to understand the effect of die size on sintering process. Optimization of dispensing pattern and die attach process challenges of thin die attachment were discussed in details in this paper.

High temperature endurable hermetic sealing material selection and reliability comparison for IR gas sensor module packaging

Infrared (IR) sensor module deploy for hazardous gas leakage detection is crucial to provide and maintain offshore Oil & Gas platform asset integrity and improve operational risk management by avoiding accidental disaster and mitigating risk associated with danger involve in oil production. These sensor modules must remain robust under harsh ambient environment. Hence, designing novel high temperature interconnects material bill of materials (BOM) with compatible barrier metallization [1-2] and robust hermetic sealing material further enhanced sensor reliability. By reducing BOM oxidation degradation at high ambient temperature [3-4], reliability of the sensor is maintained. For this study, the TV (test vehicle, Figure 1) consist of an Alumina (Al2O3) substrate casing which houses all the active components and is hermetically sealed with a Silicon (Si) die that acts as an IR filter. Laser and seam welding are common method of performing hermetic sealing but they suffer from low throughput issues. An investigative benchmark of various hermetic sealing methods and materials will be discussed in great details, targeting Alumina (Al2O3) to Silicon (Si) interfaces sealing. Both sealing surfaces have no metallization. Materials such as high temperature low outgassing adhesive, glass frit paste and ceramic paste will be applied on the TV via dispensing or screen printing method and their corresponding hermeticity performance of the sealing interface will be investigated. The silicon filter is 3.7 × 3.7 mm in size and will be mounted on a 3.8 × 3.8mm ceramic substrate casing. TV hermeticity degradation response (base on MIL-STD-883J Method 1014.14 which requires 10−9 cc/sec leak rate) is examined after reliability evaluation is conducted, which include Thermal Cycling (TC, −55°C to 250°C, 500 cycles) and High Temperature Storage (HTS, 250°C, 500 hours). The objective of this paper is to report the high temperature reliability performance of various benchmarked sealing materials and understand and document the degradation mechanism and hermeticity response (via MIL-STD leak test) after HTS and TC test at 250°C.

Gold-germanium laser jetting for high temperature (300°C) flip chip application

For downhole drilling applications, packages will have to endure extremely harsh conditions, which can easily reach a temperature of 300°C. At such high temperatures, the commonly adopted solder materials are lead-based as they are more readily available in paste and solder ball forms. While multiple studies have been performed on eutectic gold-germanium solder and its reliability at high temperature, little work has been done on the processing and assembly of the material into a flip chip package. This paper aims to study the feasibility of gold-germanium solder assembly through laser jetting process optimization. It is observed that Ge phase coarsening does not occur with laser jetting, compare to reflow process.

Out-of-plane connection in an orthogonal assembly

In this work, an out-of-plane connection in an orthogonal assembly is demonstrated. The proposed method for the orthogonal connection will help to overcome critical issues faced in this type of connection, such as lead transfer and bonding plane mismatch. It proposed to utilize the laser assisted soldering technique to achieve the lead transfer in the connection. Being a highly flexible probe array, it is more conformal to the tissue, minimizing tissue damage after implantation. Compared to previous works, the proposed flexible probe array has excellent flexibility and can easily conform to the shape of tissue, preventing the micromotion of probe after implantation. The measured impedance at the typical frequency of action potential (1 kHz) is about 12.8 kΩ.

Process and Reliability of Large Fan-Out Wafer Level Package Based Package-on-Package

This paper presents, the development of large multi-chip fan-out wafer level package (FOWLP) based Package-on-Package (PoP) using mold-First FOLWP integration flow for mobile applications. As part of this development, conventional mold-First FOWLP wafer reconstruction process has been optimized and selected key materials to overcome the challenges such as die shift, die protrusion, warpage. Fine pitch multi-layer RDL of LW/LS of 5µm/5µm fabrication, through mold via (TMV) formation, thin wafer handling for backside RDL and PoP assembly processes were also optimized. TMV process using laser drilling and sidewall plated Cu with polymer filling has been demonstrated. Using these optimized processes multi-chip FOWLP of 15 mm × 15 mm with double side RDL and high I/O count ~1360 I/Os at 400µm pitch was successfully demonstrated. Assembly process flow was optimized for PoP assembly on test boards, and build the PoP samples for reliability testing. FOWLP PoP samples were passed component level tests like MST L1, MST L3, HAST, MST L1+TC and board level tests 500 TCOB cycles and 30 drops of board level drop test.

MEMS WLCSP development using vertical interconnection

As the demand of MEMS device in mobile application is increased, MEMS device packaging technology is facing to the challenge to reduce the size and thickness. One of promising packaging solution to overcome this challenge is WLCSP (Wafer Level Chip Scale Package) using TSV(Through Silicon Via)[1,2,3]. A WLCSP using TSV technology is able to provide the smaller form factor as this used a vertical interconnection through Si die instead of conventional wire bonding for interconnection between Si die and substrate. However TSV process is still limited to apply various products since it has higher process and material cost compare to conventional wire bonding package. This study proposes a novel cost effective MEMS WLCSP using Si pillar structure and Cu wire, which work as a vertical interconnection to reduce the package size and thickness. This structure is able to provide a lower cost than TSV process since separate expensive process such as DRIE and Cu filling, etc. is not required to form the vertical interconnection. As a bottom MEMS device, 2D — accelerometer device was used in this study, and cap wafer was bonded on bottom wafer using Al-Ge eutectic bonding with wafer to wafer bonding technology. In this study, different EMCs were evaluated to optimize the package structure in the view point of process such as warpage, void and EMC filling in the gap. Also parametric study of mechanical simulation is performed to predict the stress level of MEMS device with process flow and package thickness.

Miniaturization of bio-fluidic package for point-of-care diagnostic

This paper introduces a new packaging concept that allows miniaturization of bio-fluidic package for micro and nanoparticle separation through dielectrophoresis (DEP). Leaf-shaped spacers were patterned at wafer level using a developmental bio-compatible photoresist through lithography processes, allowing better control of spacer profile and thickness. Interconnects were formed on ITO-coated glass and then flip-chip bonded onto the patterned die. The developed test vehicle, measured 5mm × 5mm, has 9216 electrodes arranged within a total sensor area of 3 mm × 3 mm. Experiments using colloids showed that the test vehicle is able to trap the 15μm suspended beads onto the electrodes.