Chai Tai Chong

TSV interposer fabrication for 3D IC packaging

In this paper, Through silicon via (TSV) based interposer fabrication processes for 3D stack packaging has been presented. An interposer test chip of 25 × 25 mm size, has been designed with full array TSVs of 50 um size vias at 300 um pitch. TSVs of aspect ratio 4 are formed on 8 inch wafer using DRIE process and these vias are isolated by thermal oxide, followed by barrier/seed layer of Ti/Cu deposition. TSVs are filled with solid copper (Cu) using optimized pulse reverse damascene electroplating and Cu chemical mechanical polishing (CMP) process also developed to remove the over burden copper with minimum dishing. Multi layer front side metallization process has been demonstrated using electroplated Cu as re-distribution layers (RDL) and spin-on-dielectrics as RDL passivation. Solid Cu filled TSVs are exposed at the backside of the TSVs using backgrinding and Cu CMP. Thin wafer handling process was developed for backside metallization on 200 um thick interposer wafers using support wafer with temporary adhesive bonding. Low temperature dielectric process has been optimized for backside via passivation to isolate the vias from surrounding silicon and backside RDL process as temporary adhesive can not withstand for high temperature processes. The support wafer is de-bonded by sliding at high temperature, followed by cleaning of temporary adhesive material on the front side of interposer wafer using cleaning chemical. TSV interposer of 200um thickness has been fabricated successfully and the vias are in very good connectivity from the top to the bottom. Complete interposer fabrication process issues and solutions have been discussed.

Effect of TSV interposer on the thermal performance of FCBGA package

In this paper, the effect of TSV (Through Silicon Via) parameters on the equivalent thermal conductivity of TSV interposer and the effect of the TSV interposer on the thermal performance of the package have been elaborated. The modeling approach using in this paper includes compact modeling for the package and detailed modeling for the TSV interposer. The objective of compact modeling is to study the effect of TSV interposer on thermal performance of the package, while the objective of detailed modeling is to extract the equivalent thermal conductivity of TSV interposer which is used for compact modeling. The proposed package in this study includes a large die with fine pitch, a silicon interposer with TSV, a 1-2-1 buildup substrate and a PCB board. In addition, to evaluate the thermal performance of the proposed package, a similar package without the TSV interposer is also modeled in this study for comparison. The results of detailed modeling show that the equivalent thermal conductivity of TSV interposer can be increased by reducing the pitch and via ratio of TSV, as well as increasing the plating thickness of partial filled TSV and using highly conductive filler material. Furthermore, the results of compact modeling reveal that the proposed TSV interposer improves the thermal performance of the package. The thermal resistance of the package decreases when the interposer size and thickness increase, and the equivalent thermal conductivity of TSV interposer has negligible effect on thermal performance of the package.

Design and fabrication of a reliability test chip for 3D-TSV

A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.

Development of High Density Fan Out Wafer Level Package (HD FOWLP) with Multi-layer Fine Pitch RDL for Mobile Applications

Recently, Fan-out Wafer Level Packaging (FOWLP) has been emerged as a promising technology to meet the ever increasing demands of the consumer electronic products. However, conventional FOWLP technology is limited to small size packages with single chip and Low to Mid-range Input/ Output (I/O) count due to die shift, warpage and RDL scaling issues. In this paper, we are presenting new RDL-First FOWLP approach which enables RDL scaling, overcomes the die shift, die protrusion and warpage challenges of conventional FOWLP, and extend the FOWLP technology for multi-chip and high I/O count package applications. RDL-First FOWLP process integration flow was demonstrated and fabricated test vehicles of large multi-chip package of 20 x 20 mm2 with 3 layers fine pitch RDL of LW/LS of 2μm/2μm and ~2400 package I/Os. Two Through Mold Interconnections (TMI) fabrication approaches (tall Cu pillar and vertical Cu wire) were evaluated on this platform for Package-on-Package (PoP) application. Backside RDL process on over molded Chip-to-Wafer (C2W) with carrier wafer was demonstrated for PoP applications. Laser de-bonding and sacrificial release layer material cleaning processes were established, and successfully used in the integration flow to fabricate the test vehicles. Assembly processes were optimized and successfully demonstrated large multi-chip RDL-first FOWLP package and PoP assembly on test boards. The large multi-chip FOWLP packages samples were passed JEDEC component level test Moisture Sensitivity Test Level 1 & Level 3 (MST L1 & MST L3) and 30 drops of board level drop test, and results will be presented.

Challenges and approaches of TSV thin die stacking on organic substrate

The requirements for high density packaging such as smaller form factor, high performance and multi functionality electronics products have resulted in electronics industry moving towards 3D System in package technology (3D SIP). Some of the main advantages of 3D SIP packaging are high volume applications, smaller form factor, better connectivity between components in a 3D package, lower noise, lower power consumption and higher operating frequencies [1]. A 3D package is a cost effective solution as it helps to save placement and routing area on board using several IC process in the same module. A stacked die SiP package offers flexibility in combining die from different fab processes into a single package. Board area savings are realized by stacking the die vertically vs a side by side approach. This package technology is mainly used where X-Y size constraint is the critical requirement. Some of the key technologies needed to enable chip stacking include silicon through-vias and high-density lead-free interconnects [2]. In the paper, 2 different reflow approaches are used for the 3 die stacked flip chip assembly (i) sequential reflow and (ii) 3 die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids and bonding alignment is addressed in this paper. In addition, a simple D.O.E was conducted to understand the effect of bond force on thin die stacked assembly Pb-free microbumps is also reported. Results showed that optimum bond force is important to ensure no die cracks during flip chip bonding for 3 layer stacked die. In addition to the DOE conducted to understand the effect of bonding parameters on thin stacked die assembly, the selection of flux in terms of flux tackiness, flux for good solder wetting and minimum solder voids in the flip chip assembly were also addressed in this work. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip on chip flip chip bonding is usually about 15µm to 20µm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore it is important to evaluate flowability, bleeding of the underfill and the void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly was discussed in this paper. Finally moldable underfill is then used to encapsulate the 3 layer stacked chip on the substrate.

Copper wire bond reliability evaluation using a modular test chip

The use of copper wire for wire bonding integrated circuits (ICs) has increased significantly in recent years, driven mainly by the dramatic increase in the cost of gold. The technical advantages and limitations, particularly with respect to reliability, of copper for wire bonding, compared with gold, have been widely reported. This paper describes reliability studies comparing on copper, palladium coated copper and gold wires using a dedicated test vehicle comprising a modular test chip with multiple daisy chains and corrosion sensors in a BGA package. The reliability tests were High Temperature Storage (HTS), 1000 hours at 150 ºC, Thermal cycling (TC) from 1000 cycles from −40 ºC to + 125 ºC, Temperature Humidity Bias (THB), 1000 hours at 85ºC/85% RH, 20 V applied, and unbiased HAST. It was found that performance was strongly dependent on the wire type and mold compound. Copper wires with one mold compound having a higher chlorine level (12mmm), showed high leakage currents and rates of failure during THB. Both copper and palladium coated copper wires with a different mold compound showed high rates of failure during thermal cycling.

Heterogeneous Three-Layer TSV Chip Stacking Assembly With Moldable Underfill

This paper reports the study of 3-D die stacking of three chips through-silicon-via (TSV) interconnections. Two different reflow approaches were used for the three-die stacked flip-chip assembly: 1) sequential reflow and 2) three-die stacked simultaneous reflow. The effect of the reflow approaches of the stacked die assembly with TSV on die warpage, solder wetting, solder voids, and bonding alignment is addressed in this paper. A simple design of experiment was conducted to understand the effect of bond force on thin die stacked assembly and Pb-free microbumps. Results showed that optimum bond force is important to ensure no die cracks during flip-chip bonding for three-layer stacked die. The selection of flux in terms of flux tackiness, flux for good solder wetting, and minimum solder voids in the flip-chip assembly were also addressed in this paper. Low standoff for microjoint assembly often poses a challenge for underfill dispensing process. The standoff between the microbump joint of the chip-on-chip flip-chip bonding is usually ~15-20 μm. The dispensing space is tight and often with limitations on the area where underfill fluids can be dispensed. Therefore, it is important to evaluate the flowability, bleeding of the underfill, and void formation in the underfill for stacked die assembly. The impact of these various factors on the stacked die assembly is discussed in this paper. The reliability of a pyramidal shape three-layer stacked TSV die package was studied by both experiments and finite-element analysis (FEA). The originally designed microbumps were located peripherally around the edge of the die, which induces a concentrated bending force on the lower die when stacking the upper die. FEA simulation results showed that such bump design induces large stress and deflection in the lower die during die stacking process. A new bump layout design has been optimized with some dummy bumps added on the central area of the die to support bending force induced by die stacking. The new design significantly reduces die stress and deflection. A moldable underfill was then used to encapsulate the three-layer stacked chip on the substrate.

Development of low profile fan out PoP solution with embedded passive

Currently PoP (Package on Package) has become a main stream of 3D integration for logic devices such as baseband and application processors with high performance memory in mobile application. This PoP has an advantage of a smaller package size with high functionality due to stacking of two different packages. However a conventional PoP with PCB substrate has a limitation to meet the recent requirement of a low profile with high performance in the thin mobile application. A fan out wafer level packaging is one of promising solution to meet a low profile with high performance. The direct solder attach on the RDL layer in the wafer level package provide a low profile package and RDL formation beyond Si die area provide a high performance with allowing higher solder ball counts. Also an embedded passive into fan out wafer level package is able to provide the better performance as well as flexibility to extend to SiP (System in Package). In this study, a low profile fan out Package on Package was successfully demonstrated with 14.0×14.0mm of a bottom package and 8.0×8.0mm of top package as well as embedded passives. The top and bottom package were electrically connected through TMV (Through Mold Via) with electro-less plating. TMV (Through Mold Via) was characterized with various EMC materials such as filler size, contents and resin material. The optimization of passive component location in term of process and reliability was performed using mold flow simulation. Also an assembly process was developed to minimize the package warpage using thermo-mechanical simulation.

Study on mold flow during compression molding for embedded wafer level package (EMWLP) with multiple chips

The rapidly increasing demand of embedded wafer level package (EMWLP) due to its advantages, smaller form factor and flexibility in system level integration leads to the development of reconstructed wafer level encapsulation. The reconstructed wafers are encapsulated with epoxy molding compound using compression molding. Due to EMWLP advanced applications, there is a need to use multi chips with different layout in a single package. The overall reconstructed wafer design then became complex that eventually leads to asymmetrical chips layout within the wafer. One major challenge in molding of reconstructed wafer with multi-chip layout was the incomplete filling due to imbalance mold compound flow during compression molding. This study was conducted to determine the actual mold compound flow during compression molding of EMWLP with multi chips layout. Mold flow studies has been carried out on different multi-chip layouts using ANSYS Poly flow/Fluent software and results revealed that asymmetrical chips layout had imbalance mold flow response. The result of the mold flow simulation was then compared to the actual mold compound flow during compression molding by performing intentional short shots at different mold filling stages. It was confirmed that actual molding with asymmetrical chips layout also resulted to unbalance mold filling. The flow of the molding compound in areas with wider gaps was faster compared to areas with narrow gaps. This suggests that the chips layout determines the actual mold compound flow during compression molding. Balanced mold compound flow was achieved by re-arranging the chips into a symmetrical layout. In addition, this paper also shows that by changing the dispensing pattern to oval shape, the actual mold compound flow on asymmetrical chips layout became balanced. The mold flow simulation results with different chips layout were validated with experimental mold compound flow tests. The simulation and experimental results revealed that the chips layout and mold compound materials dispensing pattern are critical to achieve excellent molding quality results.

Fine pitch copper wire bonding process optimization with 33µm size ball bond

Gold wire bonding is widely used as the electrical connection or interconnection between the semiconductor component (die) and the package. Bond pads pitch on the device chips are reducing continuously as device technology is moving towards nano-IC technologies. Gold wire is not suitable in the case where the bond pad pitch is less than 50µm because of golds lower intensity and stiffness [1]. Recently, copper wire becomes more and more popular in industry due to the lower in price compare to gold wire and also better electrical performance [2]. Copper wire can also be suitable for fine pitch wire bonding due to its properties. The challenge of Cu wire bonding is obtaining its process window without compromising on it quality. This paper specifically discuss the critical copper wire bonding parameters for 50µm fine pitch bond pads on stress sensor chip with aluminum pad of 1.5µm thickness using 4N copper wire of 0.7mils from Heraeus. The three main critical parameters discussed in this work are ultrasonic power, time and force. The wire bonding process parameters are optimized to achieve ball size of 33µm and ball height of 8–10µm with reasonable Al remnant under wire bond ball. To avoid the copper oxidation in the sparking process, the copper-kit is used to provide the forming gas shielding with a flow rate of 0.6–0.8l/min during sparking process. Destructive tests such as ball shear and wire pull test are used to check the bonding quality. Failure modes are analysed using high power optical microscope. Focus Ion Bean (FIB) and Scanning Electronic Microscope (SEM) are used for microsectioning on the first bond location of the samples to analyze aluminum remnant and aluminum splash.