Sharon Lim

Wafer level embedding technology for 3D wafer level embedded package

This paper presents the development of wafer level embedding process for a three dimensional (3D) embedded micro wafer level package (EMWLP). Wafer level embedding process was carried out by using compression molding machine and low-cost granular epoxy molding compound (EMC). Various molding process parameters such as molding time and temperature and three EMCs of different CTEs were analyzed to achieve reliable 3D EMWLP. Several molding process issues, such as warpage, die-sweep, EMC penetration, and die-shift, were faced during embedding process development. A large warpage of more than 1 mm and die-shift of more than 600 µm were found to occur in reconstructed molded wafer. Wafer level embedding process was optimized to reduce warpage and die-shift problems. A significant reduction in warpage (∼ 30 %) and die-shift (∼ 88 %) were achieved after embedding process optimization. The detail of process optimization is presented in the paper. Reconstructed molded wafers were subjected to various reliability tests, such as thermal cycle (TC), moisture sensitivity test-level 3 (MST-L3), and highly accelerated stress test (HAST). Scanning acoustic microscopy (SAM) analysis of molded wafers was carried out to analyze the void formation and delamination in molded wafers. No major void or delamination was observed in reconstructed wafer after molding as well as after reliability tests.

Embedded wafer level packages with laterally placed and vertically stacked thin dies

Two embedded micro wafer level packages (EMWLP) with (1) laterally placed and (2) vertically stacked thin dies are designed and developed. 3D stacking of thin dies is illustrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10mm × 10mm × 0.4mm and solder ball pitch of 0.4mm. As part of the work several key processes like thin die stacking, 8 inch wafer encapsulation using compression molding, low temperature dielectric with processing temperature less than 200 °C have been developed. The developed EMWLP components successfully pass 1000 air to air thermal cycling (−40 to 125 °C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (≫ 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL and package thicknesses can lead to designs with improved mechanical reliability.

Process Development and Reliability of Microbumps

The use of flip-chip bonding technology on gold-tin (AuSn) microbumps for flip-chip packaging is becoming increasingly important in the electronics industry. Some of the main advantages of AuSn system over solder flip-chip technology are suitability for very fine pitch interconnection and fluxless bonding. Fluxless flip-chip assembly is in demand especially for medical applications and optoelectonics packaging. Here, we report the assembly process development of a silicon stacked module assembled with AuSn microbumps to meet the stringent reliability. The effects of bond pressure distribution, bond temperature and alignment accuracy were found to be critical in this stacked silicon using AuSn microbumps. A three-factor design of experiment was carried out to investigate the effects of assembly parameters such as bonding pressure, temperature and time on contact resistance and AuSn solder wetting on the electroless nickel and gold under bump metallization. Results showed that higher bond force is undesirable and contributes to passivation cracking and deformed AuSn joint with AuSn solder being squeezed out of the joint during bonding. The reliability result of the flip-chip assembly of stacked silicon module using AuSn microbumps was presented.

Structure Design Optimization and Reliability Analysis on a Pyramidal-Shape Three-Die-Stacked Package With Through-Silicon Via

In this paper, the reliability of a pyramidal-shape three-die-stacked package with through-silicon via (TSV) is studied experimentally and numerically. The initially designed microbumps are located peripherally along the edge of the TSV die, which induces a concentrated bending force on the lower die when the upper die is stacked. Finite-element (FE) simulation results show that such bump layout induces large stress and deflection in the lower die under the die-stacking process. Three-point bend tests were conducted to determine the die strength. Die-stacking experiments were also carried out. The experimental results show that the bottom die cracks when the middle die is stacked and the middle die cracks when the top die is stacked even with a small stacking force. Consistent results have been obtained among FE simulation, die strength bend test, and die-stacking experiments. An optimal bump layout design is proposed, which adds some dummy bumps on the central area of the die to support the bending force induced by the die-stacking process. The optimal design significantly reduces the die stress level and deflection. Finally, a successful die-stacking process is achieved even using a larger stacking force.

Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device

A two-die stacked silicon module with TSV has been developed in this work. Thermal-mechanical analysis has been performed and TSV interconnect design is optimized. Multiple chips representing different functional circuits are assembled using flip chip interconnection methods. Silicon carrier is fabricated using via-first approach, the burrier copper via is exposed by special backgrinding process. A two-dimensional plane strain analysis using the global-local technique, based on St. Venants principle, is performed on the diagonal cross-section of the wafer. The thermal-mechanical modeling has shown that the shear stress Sxy at the micro-bump, compressive stress Sy at the interconnection and shear stress Sxy at the TSV are reduced for off-pad via as compared to on-pad via. This is because the CTE mismatch between the micro-bump and TSV is no longer effective when the TSV is offset. Also the work presented that the offset distance of the off-pad via does not have an impact to the compressive stress Sy and shear stress Sxy at the interconnection. There are also no significant changes in the shear stress Sxy at the TSV as the off-pad via moves outward to the die edge. As we knows that the bending stress Sx is a major factor contributing to die cracking due to coefficient of thermal expansion (CTE) mismatch. Our simulation results showed that the bending stress Sx of the top die and bottom die was not affected by increasing the offset distance of the off-pad via even to the die edge. Thus it is an advantage to plate the through-silicon-via away from the micro-bump to avoid stresses complication arises from CTE mismatch.

Development of solder replacement flip chip using anisotropic conductive adhesives

With the continual drive towards package miniaturization, flip chip assembly using anisotropic conductive adhesives (ACAs) is fast emerging as one of the potential interconnect technology solutions in the fine pitch application space. In this paper, we report the process development of solder replacement flip chip at 120/240/spl mu/m bump pitch using ACAs for mid I/O applications. Optimized ACA cure profiles were derived based on die shear test results. The cure time for anisotropic conductive paste (ACP) was found to be 2/spl times/ longer than anisotropic conductive film (ACF) to achieve the same die shear strength for a given curing condition. Prolonged curing at 220/spl deg/C was found to enhance the die shear strength. Consistent resistance reading was used as a criterion for ACA bond force selection. Generally, uncoined Au bumps was found to have lower and more stable resistance due to contact between the Au bump and substrate pad. As compared to unfilled ACF, silica filled ACP exhibited better contact resistance stability during temperature cycling (TC) and temperature humidity (TH) tests.

Thermal Characterization of Both Bare Die and Overmolded 2.5-D Packages on Through Silicon Interposers

The next generation of heterogeneous integration requires 2.5-D packages on through silicon interposer (TSI) as enabling technology for less signal delay, faster speed, and more functionality. In the meantime, the introduction of multiple chips on interposer tends to increase the heat density with added interconnect complexity, which requires systematic thermal analysis and characterization. In this paper, thermal characterization of 2.5-D packages on TSI is reported in both bare-die package and overmolded package formats. The test vehicle consists of two dummy chips and thermal test die assembled on the same interposer of 18 mm × 18 mm × 0.1 mm through the flip chip bumping and joining process. A thermal test chip of 5.08 mm × 5.08 mm is built in with heaters and diodes for thermal characterization. Thermal measurements are conducted for thermal resistances from junction to the ambient, from junction to the board, and from junction to top casing. Measurement accuracy is improved through distributed through silicon via network, multidie temperature monitoring and uncertainty analysis and minimization. It is found that the overmolded package has lower thermal resistances than the bare die package. In addition, the thermal resistance from the junction to the casing is also characterized with a liquid-cooled minichannel cold plate as heat sink, indicating the vast difference between bare die package and molded package. Besides experimental measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to examine the effects of overmold thickness and power dissipation from the multichips module on the interposer.

Thermal characterization and simulation study of 2.5D packages with multi-chip module on through silicon interposer

Next generation of heterogeneous integration requires 2.5D package on interposer as enabling technology for less signal delay, faster speed, and more functionality. In this work, thermal characterization and simulation of a 2.5D package with multi chips on through silicon interposer (TSI) are reported. Two dummy chips with chip sizes of 7.6×10.9mm and 8mm×8mm, respectively, are arranged on the interposer through the flip chip bumping and joining process. To facilitate the thermal characterization, a thermal test chip of 5.08×5.08mm is embedded on the same interposer for thermal test and simulation validation. In either molded or bare die BGA package format, the thermal test vehicles are brought for thermal characterization, including Theta JA Theta JB measurement conforming with the JEDEC standards. It is found that the overmolded package has slightly lower thermal resistances than the bare die package. In addition, the Theta JC, namely, the thermal resistance from the junction to the top casing is also characterized through a high performance cold plate. Besides the thermal measurements, thermal simulation models under different boundary conditions are established, respectively, to compare with the thermal measurements. Good agreements are generally achieved between simulation and measurements. Further simulation is also conducted to study the effects of overmold thickness and power dissipation from the multi chips module on the interposer.

Thermo-compression bonding for 2.5D fine pitch copper pillar bump interconnections on TSV interposer

The use of portable electronic devices like smart phones and tablets results in high demand for more function, smaller dimensions and reduced power consumption requirements. To meet these challenges, electronic package design uses thinner chips with fine pitch bumping. There is active development in 2.5D and 3D IC packages with through silicon via (TSV). Tighter interconnection in addition to the increased density in the circuit in 2.5D and 3D IC systems provide higher performance with lower power consumption [1]. In addition, there is increased in the demand for fine pitch copper pillar bumping due to the lower silicon node, chip size reduction and TSV technology. Fine pitch interconnections are required in 2.5D and 3DIC integration for the demands of electrical continuity and high performance. In the existing interconnection methods, solder micro bumps have received a great deal of attentions because of its low material and process cost [2]. The major difference of copper pillar FC bonding process comparing to traditional FC bonding process is the reduction of the solder volume on each solder bump. As a result, there is no advantage of self-alignment of the solder during solder reflow process. Flip-chip bonder having accurate chip placement capability is needed to ensure good solder joint formation. Conventional reflow method is still applicable for sizable solder bump of diameter being greater than 100 μm and larger than 150μm pitch [3]. The post underfill processes such as capillary underfill (CUF) and molded underfill (MUF) can be followed after the solder joints are formed. On the other hand, when the pitch of bumps and/or the thickness of the FC go down further, FC with copper pillar bumps bonded by TC process would be one of the solutions for fine-pitch FC applications. It has been shown that the bump pitch can be reduced to as small as 50 μm (inline pitch). This process also allows for better control on the solder squeezed out effect. However this process requires tight control on (i) the planarization between the FC and the bonding substrate and (ii) the stand-off of each solder joint. Good process parameters have to be established to ensure no solder collapse or open joint.

Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages

Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.