Nicolas Guitard

BIMOS transistor and its applications in ESD protection in advanced CMOS technology

BIMOS transistor is a useful device and now compliant in advanced CMOS technology. This device acts with high controlled current gain. Thus, it is an efficient candidate for Electrostatic Discharge (ESD) protection. Moreover it is well known that ESD protection for advanced CMOS technologies is a major challenge due to down-scaling which introduces a reduction of the intrinsic robustness. This paper introduces the BIMOS ESD approach with simulations in 45nm. Silicon measurements are performed on 32 nm CMOS high k metal gate.

EOS characterization methodology applied to disable feature of ESD power clamps

This work presents an EOS characterization methodology for ESD clamps. BigFET-based and SCR-based power clamps with and without disable feature are characterized. Thanks to the proposed characterization methodology, robustness comparison is provided for the different ESD clamps, giving insights on improving IC robustness against undesired triggering during EOS events.

Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes

Abstract A new SCR-based device for ESD protection is presented through TCAD simulation and experimental results on a standalone configuration and for a power supply ESD clamp strategy. The new device can turn-off even if the voltage power supply is applied at its Anode. We use 3D TCAD simulation for understanding its turn-on and turn-off behavior. At the same time, the flexibility of the EOS test bench allows for standalone and power supply clamp characterizations at chip level at ambient and high temperature.

ESD protection structure enhancement against Latch-Up issue using TCAD simulation

During IO qualifications LUP tests in CMOS28nm Bulk technology, undesired ESD structure triggering has been found to be the root cause of LUP fails. Deeper test analysis identifies the combination of IOs abutment sequence that generate the fail. The understanding of the phenomenon is investigated through a specific TCAD simulation set-up.

Ultracompact ESD Protection With BIMOS-Merged Dual Back-to-Back SCR in Hybrid Bulk 28-nm FD-SOI Advanced CMOS Technology

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip.