John Viaene

Low leakage high breakdown e-mode GaN DHFET on Si by selective removal of in-situ grown Si 3 N 4

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

Si Trench Around Drain (STAD) technology of GaN-DHFETs on Si substrate for boosting power performance

We report on the first measurement results to obtain over 2 kV breakdown voltage (VBD) of GaN-DHFETs on Si substrates by etching a Si Trench Around Drain contacts (STAD). Similar devices without trenches show VBD of only 650 V. DHFETs fabricated with STAD technology show excellent thermal performance confirmed by electrical measurements and finite element thermal simulations. We observe lower buffer leakage at high temperature (100°C) after STAD compared to devices with Si substrate, enabling high temperature device operation.

Reliability of AlGaN/GaN HEMTs: Permanent leakage current increase and output current drop

In this work we report on the two most common failure modes for AlGaN/GaN-based HEMTs: the gate leakage increase and the output current drop. First, by performing step-stress experiments in function of the step-time (tSTEP) we show that the critical voltage for the increase of gate leakage current depends on the tSTEP and is not associated with a permanent drop of the output current. Consequently, identification of the critical voltage by means of step-stress is not meaningful per se since it depends on the tSTEP used. Second, we show that during high power stress at high voltage a permanent output current drop occurs. The failure analysis reveals the formation of crystallographic defects in the AlGaN layer along the whole width of the gate, in agreement with the inverse piezoelectric theory. However, in contrast to the degradation model based on the inverse piezoelectric effect, these defects do not aid the leakage of electrons from the gate toward the drain electrode since the output current drop is not associated with an increase of the gate leakage current. Therefore, combining the outcome of the two experiments, we suggest that the two most common failure modes are not correlated despite both might concur to the device degradation. Finally, an excellent stability is shown for devices with reduced Al content in the AlGaN barrier, highlighting the fundamental role of strain on reliability of AlGaN/GaN-based devices.

GaN power amplifier design based on artificial neural network modelling

GaN field effect transistors (FETs) have a strong potential for high-power applications. However the RF performance of these devices often experiences limitation due to trapping effects and self-heating. These complicate the development of accurate large-signal models for GaN FETs. To simplify this process, a state-space modelling technique using an artificial neural network (ANN) is used in this work to model the large signal behaviour of the GaN device. In this way, the model is constructed directly from large-signal measurement data collected while the device is in an operating mode close to its application, i.e., class AB power amplifier (PA). To demonstrate the approach, a hybrid power amplifier based on GaN FETs was designed and fabricated. The good agreement between measurements and simulation results verifies the proposed approach. It is the first time that this modelling approach is used in circuit design.

GaN-on-Si power field effect transistors

GaN-on-Si has become the most promising technology for next-generation power switching devices to overcome intrinsic Si limits for high temperature operation, high efficiency at high operating voltage, and high switching frequency. Depletion-mode devices are already offering more than one order of magnitude lower specific on-resistance above 600V. Further, we have recently demonstrated e-mode devices (Vt>0.5V) with high current density, thanks to a unique in-situ SiN passivation approach. This in-situ SiN layer is further shown to be a key parameter for device stability at elevated temperatures, significantly enhancing the device reliability in high temperature accelerated lifetime tests.