Mostafa Elmala

A 90-nm CMOS Doherty power amplifier with minimum AM-PM distortion

A linear Doherty amplifier is presented. The design reduces AM-PM distortion by optimizing the device-size ratio of the carrier and peak amplifiers to cancel each others phase variation. Consequently, this design achieves both good linearity and high backed-off efficiency associated with the Doherty technique, making it suitable for systems with large peak-to-average power ratio (WLAN, WiMAX, etc.). The fully integrated design has on-chip quadrature hybrid coupler, impedance transformer, and output matching networks. The experimental 90-nm CMOS prototype operating at 3.65 GHz achieves 12.5% power-added efficiency (PAE) at 6 dB back-off, while exceeding IEEE 802.11a -25 dB error vector magnitude (EVM) linearity requirement (using 1.55-V supply). A 28.9 dBm maximum Psat is achieved with 39% PAE (using 1.85-V supply). The active die area is 1.2 mm/sup 2/.

A highly linear filter and VGA chain with novel DC-offset correction in 90nm digital CMOS process

This paper presents a complete base-band chain for current and emerging WLAN in 1.4V 90nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 1/10/100MHz filter and five VGA stages. The design is DC-offset free and uses optimized Gm stages for linearity and low voltage operation. IIP3 is 2dBm @ 13.5dB minimum gain, while dissipating 13.5mW.

A 1.4V, 13.5mW, 10/100MHz 6/sup th/ order elliptic filter/VGA with DC-offset correction in 90nm CMOS [WLAN applications]

This paper presents a complete base-band chain for WLAN applications in 1.4 V 90 nm CMOS. The chain consists of a 6/sup th/ order elliptic Gm-C 10/100 MHz filter and five VGA stages. The design is DC-offset free and uses optimized transconductance for linearity and low-voltage operation. Moreover, the integrators in the filter are compensated for losses through a frequency transformation. The IIP3 is 2 dBm at 13.5 dB minimum gain, while dissipating 13.5 mW.

A 90nm CMOS Doherty Power Amplifier with Integrated Hybrid Coupler and Impedance Transformer

An OFDM capable Doherty PA is implemented in 90 nm CMOS with integrated quadrature hybrid and impedance transformer. The two amplifiers are optimized to minimize AM-PM distortion. The PA achieves 25 dBm Psa, using 1.4 V supply with 24% PAE, and operates over 1 GHz of frequency range (from 4 GHz to 5 GHz). 3 dB to 6 dB back-off from P1dB is required to achieve -25 dB measured EVM across this band, making it suitable for WLAN and WiMAX applications. The measured AM-PM distortion varies from 4deg to 12.5deg across the 1 GHz range.

A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS

A 5GHz 2times2 MIMO transceiver in 90nm CMOS supports spatial multiplexing and diversity, achieving 54/108Mb/s with -75/-63dBm sensitivity for an AWGN/25ns-Rayleigh channel, respectively. Each RX draws 120mA from a 1.4V supply. Each 3.3V 5GHz PA delivers +16/+13dBm average power with -25/-27dB EVM in 1times1/2times2 modes, respectively. The system-in-package including microstrip front-end matching on a flip-chip package occupies a die area of 18mm2

A 1.4V, 2.4/5 GHz, 90nm CMOS system in a package transceiver for next generation WLAN

We present a 2.4/5GHz system in a package transceiver with integrated 5GHz PA and 10-100MHz signal bandwidth, suitable for next generation WLAN applications. The RXs achieve better than -71dBm sensitivity for 64 QAM while drawing 120mA from a 1.4 supply in a 90nm CMOS process. The integrated 3.3V, 5GHz PA delivers 9dBm average power with an EVM better than -25dB. The transceiver incorporates de-convolved calibration of quadrature mismatches in the transmitter and receiver for improved performance and yield. Micro strip passives are integrated into a flip chip package for both LNA and PA matching elements.

A 5GHz, 108Mb/s 2×2 MIMO CMOS Transceiver

MIMO wireless transceivers employ multiple antennas and advanced digital signal processing to achieve higher data rates and superior link reliability compared to their single-antenna counterparts. This paper presents a 2times2 MlMO 5 GHz WLAN transceiver implemented in 90 nm CMOS. Crosstalk between the different MIMO channels is shown to have a detrimental effect on MIMO performance. Such crosstalk can occur at the radio channel, between the antennas, and at the radio IC. Several architectural and circuit techniques are described that minimize crosstalk between the multiple radio chains co-existing on the same silicon die. Measurements results demonstrate the increased data rate of the fabricated system compared with a conventional single-antenna system