Teva Stone

A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution delays with embedded clocking via superposition of clock in the common-mode across two differential pairs was also explored. A test device was fabricated in TSMCs 40 nm LP CMOS process and performance measurements indicate substantial margin improvements, even when the matched source-synchronous system is subjected to realistic source SJ and independent PSIJ noise. Comparable performance was also achieved with embedded common-mode clocking with matched peak swings, indicating it as a potential solution for pin-constrained designs.

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface

A 800 Mb/s to 3.2 Gb/s memory interface is designed that achieves 30% improved energy efficiency by eliminating idle mode power completely. The link is similar to a standard DDR architecture with the addition of a fast-lock DLL on the memory side that wakes up from 0 mW and locks within 3 clock cycles consuming 24 mW with residual timing error less than 33 mUI. Following initial lock, the DLL operates in a closed loop to compensate for V,T drift consuming 6 mW @ 1.6 GHz including a replica buffer. By incorporating an injection locked oscillator inside the loop, the DLL provides PLL like high frequency input jitter filtering, and corrects ±10% DCD without an additional duty cycle correction loop.

A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching

A dynamic rate adjustable interface is designed a 40-nm LP CMOS process. On-the-fly dynamic rate change is enabled by an all-digital frequency multiplier that detects a reference frequency change, and accordingly provides 4× multiplied clock without any idle time. The clock multiplier, along with matched source synchronous clocking and clock equalization, allows blind reference clock shifting to scale the data rate from 1.6 to 6.4 Gb/s within 6.125ns without idle time or bit errors during transitions. The interface efficiency is 2.6 mW/Gb/s @6.4 Gb/s & 3.4 mW/Gb/s @3.2 Gb/s when using reduced clock swing and external transmitter swing at the reduced data rates.

A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces

A 5Gb/s signaling system was designed and fabricated in TSMCs 40nm LP CMOS process. A new clock/data skew minimization technique with a source-synchronous transmit clock delay line and integrating receiver tolerates high frequency transmit clock jitter and supports rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution via embedded clocking with superposition of clock in the common-mode was also explored.