Byeung-Chul Kim

PRAM cell technology and characterization in 20nm node size

We reported characteristics of 20nm PRAM cell. Optimization of diode integration process and improved implantation technology were used to satisfy the required diode on-current (Ion) with low off-current (Ioff). Confined cell structure and novel bottom electrode (BE) materials were developed to reduce a reset current (Ireset) below 100uA. Using the advanced technologies, we successfully produced fully integrated 20nm node size PRAM device for the first time.

A process technology for 1 giga-bit DRAM

In this paper, we present a giga bit density DRAM technology based on the state-of-the-art technologies. A DRAM with 1 giga bit density design rule is fabricated featuring Shallow Trench Isolation (STI), TiSi/sub x/ gate, Self-Aligned Contact (SAG), and simple stack capacitor cell using (Ba,Sr)TiO/sub 3/ (BST) as a dielectric material. A reliable and highly manufacturable process is established which satisfies the stringent requirement for the next generation memory devices such as 1 Gbit DRAM and beyond.

Reliability perspectives for high density PRAM manufacturing

This paper discussed the key reliability issues for manufacturing high density phase change memory (PRAM). There are its own unique phenomena, such as resistance fluctuation, structural relaxation and crystallization, which are closely correlated with the device reliability characteristics, including data retention, cycling endurance, and write disturbance. Optimizing material composition and controlling doping concentration and minimizing variability of physical dimensions can improve the reliability issues. Above all, isotropic dimension scaling along with writing current scaling is essential for continuing scaling down below 20nm node.

Current status and future prospect of Phase Change Memory

This paper reviews recent progress and future outlook of PRAM as a promising candidate for emerging non-volatile memory. Electrical characteristics and reliability issues of PRAM with scale-down of the device dimension are discussed. Despite remarkable progress of PRAM properties in recent last decades, there are still several fundamental issues to resolve for broadening its application area. Several suggestions to overcome these property issues are introduced with recent experimental results.

Active Width Modulation (AWM) for cost-effective and highly reliable PRAM

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔIPGM, is reduced from 17.8% to 0.82%, and that of a write energy, ΔEPGM, from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, IRESET, for sub-40 nm PRAM technology and so on.

Isolation merged bit line cell (IMBC) for 1 Gb DRAM and beyond

The Isolation-Merged Bit Line Cell (IMBC) structure was investigated with 0.20 /spl mu/m advanced Deep UV lithography as a candidate cell structure for 1 Gb DRAM and beyond. Better photo margin owing to the improvement of bit-line and global topology, easy formation of cell capacitor, simple process and better process margin were accomplished in IMBC. The electrical characteristics of IMBC was comparable to that of the conventional Capacitor Over Bit line (COB) cell. Moreover, the bit line coupling noise was significantly reduced in IMBC compared with COB. Thus, IMBC is a promising cell structure for 1 Gb DRAM and beyond.