Byung-Gil Jeon

An embedded nonvolatile FRAM with electrical fuse repair scheme and one time programming scheme for high performance smart cards

An embedded ferroelectric random access memory (eFRAM) with an electrical fuse (e-fuse) repair scheme, in which the repair information can be electrically programmed, was successfully developed for a high performance smart card. From the viewpoints of security and cost-efficiency, the e-fuse repair scheme with ferroelectric memory cell is the best way to improve the yield of the smart card. We realized a flexible and efficient repair scheme by controlling it with repair signals and the addresses. The successful operation of the e-fuse repair scheme was confirmed and the fixed attempt ratio was over 95%. Additionally, the one time programming cells were embodied by modifying the control scheme of the eFRAM for the smart card application. The cycle time and address access time of the eFRAM for the smart card application were 70ns and 50ns, respectively.

A 0.4 /spl mu/m 3.3 V 1T1C 4 Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit

A 0.4-/spl mu/m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric random access memory (FRAM) was developed. The FRAM relies on the use of a reference scheme optimally adapted to the entire cell population of an individual device. A simple voltage level detector protects the device against data loss during drops in supply voltage. Finally, a special test mode was implemented to optimize read pulse width. By using these techniques, a high-performance 1T1C 4-Mb FRAM was successfully developed.

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-/spl mu/m ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25/spl deg/C, 110-ns minimum cycle. The die size is 116 mm/sup 2/ using 9 /spl mu/m/sup 2/, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology.

A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.

A 1T/1C Ferrodectric RAM Using A Double-level Metal Process For Highly Scalable Nonvolatile Memory

A double-level metal, one-poly, 1T/lC 64k ferroelectric RAM has been successfully fabricated with 1.2~ conventional CMOS technology. By realizing aluminum bit line, aluminum plate line in the doublelevel metal process without degrading Pt/PZT/Pt ferroelectric capacitor and by adopting lT/lC cell archtecture, lOOns data access time was obtained at Vcc=S.OV which is faster by 40% than the commercialized 2T/2C FRAM with a single-level metal. A proper annealing processes was proved to be the key for the recovery of the ferroelectric capacitor degradation caused by the double-level metal integration process.

A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme

A 4 Mb 1T1C FeRAM with a common-plate folded bit-line architecture achieves low noise without cell area penalty in nonvolatile ferroelectric RAM. The decoder of common plate scheme reduces area to about 62% that of a conventional separate-plate scheme. The chip area is reduced by 9.2% to 111 mm/sup 2/. The bit-line capacitance imbalance is resolved without speed loss or area penalty.

A novel cell charge evaluation scheme and test method for 4 Mb nonvolatile ferroelectric RAM

This paper proposes a novel method to evaluate the real cell ferroelectric capacitor with 4 Mb nonvolatile ferroelectric RAM which has a Cell Charge Evaluation Scheme (CCES). The charge value and the distribution of the memory cell ferroelectric capacitor can be evaluated by the CCES. Additionally, it can easily screen out weak bits which have smaller charges than normal cells by using the CCES as a bit-line reference voltage generator.