Yeon-Bae Chung

A 0.4 /spl mu/m 3.3 V 1T1C 4 Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit

A 0.4-/spl mu/m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric random access memory (FRAM) was developed. The FRAM relies on the use of a reference scheme optimally adapted to the entire cell population of an individual device. A simple voltage level detector protects the device against data loss during drops in supply voltage. Finally, a special test mode was implemented to optimize read pulse width. By using these techniques, a high-performance 1T1C 4-Mb FRAM was successfully developed.

A 3.3-V, 4-Mb nonvolatile ferroelectric RAM with selectively driven double-pulsed plate read/write-back scheme

This paper presents, for the first time, a 4-Mb ferroelectric random access memory, which has been designed and fabricated with 0.6-/spl mu/m ferroelectric storage cell integrated CMOS technology. In order to achieve a stable cell operation, novel design techniques robust to unstable cell capacitors are proposed: (1) double-pulsed plate read/write-back scheme; (2) complementary data preset reference circuitry; (3) relaxation/fatigue/imprint-free reference voltage generator; (4) open bitline cell array; (5) unintentional power-off data protection scheme. Additionally, to improve cell array layout efficiency a selectively driven cell plate scheme has been devised. The prototype chip incorporating these circuit schemes shows 75 ns access time and 21-mA active current at 3.3 V, 25/spl deg/C, 110-ns minimum cycle. The die size is 116 mm/sup 2/ using 9 /spl mu/m/sup 2/, one-transistor/one-capacitor-based memory cell, twin-well, single-poly, single-tungsten, and double-Al process technology.

A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.

A novel cell charge evaluation scheme and test method for 4 Mb nonvolatile ferroelectric RAM

This paper proposes a novel method to evaluate the real cell ferroelectric capacitor with 4 Mb nonvolatile ferroelectric RAM which has a Cell Charge Evaluation Scheme (CCES). The charge value and the distribution of the memory cell ferroelectric capacitor can be evaluated by the CCES. Additionally, it can easily screen out weak bits which have smaller charges than normal cells by using the CCES as a bit-line reference voltage generator.