Mun-Kyu Choi

A 0.4 /spl mu/m 3.3 V 1T1C 4 Mb nonvolatile ferroelectric RAM with fixed bit-line reference voltage scheme and data protection circuit

A 0.4-/spl mu/m 3.3-V 1T1C 4-Mb nonvolatile ferroelectric random access memory (FRAM) was developed. The FRAM relies on the use of a reference scheme optimally adapted to the entire cell population of an individual device. A simple voltage level detector protects the device against data loss during drops in supply voltage. Finally, a special test mode was implemented to optimize read pulse width. By using these techniques, a high-performance 1T1C 4-Mb FRAM was successfully developed.

A 0.25 /spl mu/m 3.0 V 1T1C 32 Mb nonvolatile ferroelectric RAM with address transition detector (ATD) and current forcing latch sense amplifier (CFLSA) scheme

A nonvolatile 32 Mb ferroelectric random-access memory with 0.25 /spl mu/m design rules uses ATD control for SRAM applications and a common-plate folded bit-line cell scheme with current forcing latched sense amplifier for low noise level without cell area penalty.

A 3.3-V 4-Mb nonvolatile ferroelectric RAM with a selectively-driven double-pulsed plate read/write-back scheme

Summary form only given. Recently there has been a growing interest in ferroelectric RAM because of its great potential as a future nonvolatile memory. This work presents, for the first time, a 4 Mbit FRAM with novel design techniques: 1) open bitline cell array; 2) selectively-driven double-pulsed plate read/write-back scheme; 3) complementary data preset reference circuitry and relaxation/fatigue/imprint-free reference voltage generator; and 4) unintentional power-off data protection scheme. The prototype device incorporating these circuit schemes shows 75 ns access time, 21 mA active current at 3.3 V, 25/spl deg/C, 110 ns cycle. It measures 116 mm/sup 2/ with 0.6 /spl mu/m CMOS technology.

A nonvolatile ferroelectric RAM with common plate folded bit-line cell and enhanced data sensing scheme

A 4 Mb 1T1C FeRAM with a common-plate folded bit-line architecture achieves low noise without cell area penalty in nonvolatile ferroelectric RAM. The decoder of common plate scheme reduces area to about 62% that of a conventional separate-plate scheme. The chip area is reduced by 9.2% to 111 mm/sup 2/. The bit-line capacitance imbalance is resolved without speed loss or area penalty.