Byung Yong Choi

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB program schemes is proposed. A BL voltage modulated ISPP scheme was used as parallel MSB programming in order to reduce cell-to-cell interference caused by the order in which the cells are programmed. By adopting the proposed page architecture, the number of neighbor cells that are programmed after programming a selected cell in BL direction as well as their amount of T/th shift during programming can be suppressed largely without increasing memory array size. Compared to conventional architecture it leads to a reduction of BL-BL cell-to-cell interference by almost 100%, and of WL-WL and diagonal cell-to-cell interferences by 50% at the 60 nm technology node. The proposed architecture enables also to improve average MLC program speed performance by 11% compared with conventional architecture, thanks to its fast LSB program performance.

Short-channel field-effect transistors with 9-atom and 13-atom wide graphene nanoribbons

Bottom-up synthesized graphene nanoribbons and graphene nanoribbon heterostructures have promising electronic properties for high-performance field-effect transistors and ultra-low power devices such as tunneling field-effect transistors. However, the short length and wide band gap of these graphene nanoribbons have prevented the fabrication of devices with the desired performance and switching behavior. Here, by fabricating short channel (Lch ~ 20 nm) devices with a thin, high-κ gate dielectric and a 9-atom wide (0.95 nm) armchair graphene nanoribbon as the channel material, we demonstrate field-effect transistors with high on-current (Ion > 1 μA at Vd = −1 V) and high Ion/Ioff ~ 105 at room temperature. We find that the performance of these devices is limited by tunneling through the Schottky barrier at the contacts and we observe an increase in the transparency of the barrier by increasing the gate field near the contacts. Our results thus demonstrate successful fabrication of high-performance short-channel field-effect transistors with bottom-up synthesized armchair graphene nanoribbons.Graphene nanoribbons show promise for high-performance field-effect transistors, however they often suffer from short lengths and wide band gaps. Here, the authors use a bottom-up synthesis approach to fabricate 9- and 13-atom wide ribbons, enabling short-channel transistors with 105 on-off current ratio.

Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure

Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (V/sub th/) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.

SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory

For the multi-gigabit NAND flash memory, SONOS-type FinFET device with p+ gate and high-k blocking dielectric has been integrated both on the cell array and GSL/SSL for the first time. The advantages of the FinFET structure for the NAND flash application have been theoretically and experimentally demonstrated, and the results show that the 85 % improved on-cell current is achievable using FinFET device. The enhanced programming and retention characteristics of FinFET have been also presented, and modeled by the potential changes on fully-depleted body of the sub-40 nm ultra-narrow fin

Trap Layer Engineered FinFET NAND Flash with Enhanced Memory Window

This paper presents the trap layer engineered body-tied FinFET device for MLC NAND flash application. The device design parameters for high density NAND flash memory have been considered, and the advantages of FinFET structure and high-k blocking dielectric in such device have been demonstrated. Based on the WN nano-dot memory device, the trap layer engineering using nitride layer has been performed, and the results show that the memory window is improved from 2.6 V to 7.8 V by utilizing engineered trap layer at 14 MV/cm F-N programming, and it is proposed as a possible MLC NAND device structure

Retention Reliability of FinFET SONOS Device

This paper presents the retention reliability of the FinFET SONOS flash memory. By understanding the charge loss mechanisms of the SONOS structure, a new approach for the prediction of long term retention lifetime have been proposed. The comparison between the thermal-accelerated and field-accelerated lifetime has been demonstrated

Investigation on the Retention Reliability of Scaled

We investigate the retention reliability of a 51-nm-node 16-GB nand Flash cell transistor comprising SiO₂/Al_xO_y/SiO₂ inter-poly dielectric (OAO IPD). Despite the fact that OAO IPD retains low trapping rate being beneficial to retention reliability, the trap sites are located on shallow energy level, yielding a large amount of trap-assisted tunneling current at high temperature. Therefore, experimental results show two incompatible data retention characteristics of OAO IPD, namely, 33% worse <i>V</i> _TH shift at 200°C 2-h bake and 53% improved <i>V</i> _TH shift after one week at 25°C, when compared to the case of ONO IPD.

\hbox{SiO}_{2}/\hbox{Al}_{x}\hbox{O}_{y}/\hbox{SiO}_{2}

Now flash memories using poly-Si floating gate are in front of their scaling limits. Nanocrystal or nano-dot trapping memory is a candidate for one of future scaled flash memories. Many efforts with semiconductor nanocrystals such as Si or Ge have just a small memory window [1-5]. Some other experiments using metal nanocrystal have been made to improve threshold voltage shift, but their endurance and retention characteristics are not satisfied. In this work, we will report the discrete charge trapping WN nano-dots for FinFET flash memory. We also investigate whether an additional thin nitride sub-layer is useful or not. In the fabrication of body-tied FinFET Flash memory using WN nano-dots, 3.5 nm-thick SiO2 films containing nitrogen were grown by dry oxidation after the active fin formation and shallow trench isolation processes. Fin structured MOSFET has an advantage to increase the number of nano-dots per cell due to the enlarged active area. In addition, FinFET structure is expected to provide the better program inhibition characteristics owing to the superior punch-through controllability of the transistor. For the trap layer, the WN nano-dots were deposited using a pulsed nucleation layer CVD method with B2H6, WF6, and NH3 gases. WN nano-dot process is optimized through controlling gas flow rate, process temperature, and cycle numbers in the kinetically limited process regime. A cross-sectional TEM and SEM micrograph ofWN nano-dot device with very thin SiN layer with 2 nm thickness are shown in Fig.1 (a) and (b). Si fin height is almost 100 nm and gate length is 55 nm. It is clearly observed that the WN nano-dots are embedded between the thin nitride layer and control oxide(A1203 with 12.2 nm thickness). The mean size of dots and aerial density are estimated to be about 3 5 nm and lx 1012cm2, respectively. The work-function ofWN turns out to be 4.65 eV by the method in [6], and it is expected to provide 1.2 eV deeper trap sites than average trap level of SiN layer considering energy band diagram as shown in Fig. 2. For the blocking dielectrics, amorphous AlxOy layer deposited by ALD CVD process followed by post-anneal at 950°C, 30 sec to make it a crystalline phase of A1203. A1203 layer as a blocking oxide demonstrate more than 4 orders of magnitude smaller leakage current properties on annealing temperature. From EDX spectrum analysis, it is found that there is no W diffusion into the tunnel oxide after 1000°C anneal treatment. After 16V, 100[ts program stress, threshold voltage shift is measured over 4.2 V from ID-VG characteristics as shown in Fig. 3. Program and erase stresses with 16V, 100[ts and -16V, lOOms induced flat band voltage shifts, respectively. Fig. 4 exhibits the capacitance-voltage characteristics of initial, program, and erase state (a)with and (b)without thin nitride under-layer. In case of (a) with thin SiN under-layer, the AVFB is 3.84V and it is larger than that of case (b). We think that bulk traps in SiN sub-layer and WN nano-dot/SiN interface traps assist larger memory window. In addition, thin SiN layer is considered as a diffusion barrier ofW or WN atoms so that there is no degradation of tunneling oxide. Fig. 5 represents the retention characteristics ofWN nanodot FinFET (a)with and (b)without thin nitride layer. It is cleared confirmed that WN nano-dot memory cell with thin nitride sublayer has a good retention characteristics up to 105 sec at room temperature. It is considered that there are tunnel oxide degradations due to local W atom diffusion into thin oxide layer ifwe do not use SiN barrier layer. Concerning the concept of dot surface and defect level engineering, WN dot surface is so highly curved that the surface is more strained in comparison with the plane surface, which causes high defect density around each of WN nano-dots. In addition to that, WN dot has so high permittivity like a conducting sphere that the local electric field near channel area increase, which enhances the Fowler-Nordheim (F-N) tunneling probability. Consequently these are attributed to the thinning tunneling oxide and the large capturing efficiency of WN dots in case tunneling oxide degradations due to W diffusion are effectively protected. We have demonstrated the WN nano-dot/thin SiN stacked FinFET characteristics for NVM device application. WN nano-dots with thin SiN sub-layer are certainly applicable as a charge storage node.