C.-E. Chen

Total Dose Characterizations of CMOS Devices in Oxygen Implanted Silicon-on-Insulator

The total dose characteristics of CMOS devices fabricated in oxygen implanted buried oxide silicon-on-insulator (SOI) substrates with different post-implant annealing processes are studied. The threshold voltage shift, subthreshold slope degradation and mobility degradation of front channel SOI/CMOS devices are measured to be the same as those of bulk devices processed identically. Negative substrate bias lowers the threshold voltage shift of back channel SOI transistors, while not affecting the front channel characteristics. Under present processing conditions, the radiation characteristics of front channel devices are independent of the postoxygen-implant annealing temperature. Oxygen precipitates at the silicon/buried oxide interface enhance interface state generation of the back channel devices during irradiation.

Stacked CMOS SRAM cell

A static random access memory (SRAM) cell with cross-coupled stacked CMOS inverters is demonstrated for the first time. In this approach, CMOS inverters are fabricated with a laser recrystallized p-channel device stacked on top of and sharing the gate with a bulk n-channel device using a modified two-polysilicon n-MOS process. The memory cell has been exercised through the write and read cycles with external signal generators while the output is buffered by an on-chip, stacked-CMOS-inverter-based amplifier.

The effects of oxygen dose on the formation of buried oxide silicon‐on‐insulator

The effects of the oxygen dose on the microstructure and the dielectric properties of the buried oxide in oxygen implanted silicon‐on‐insulator (SOI) structures have been studied. Cross‐sectional transmission electron microscopy analyses show that the density of oxygen precipitates at the silicon/buried‐oxide interface increases with a decreasing oxygen dose when identical annealing processes are employed. Annealing studies reveal that 1275 °C anneals annihilate the oxygen precipitates. A longer annealing time is required to achieve an oxygen‐precipitate‐free silicon layer in an SOI substrate implanted with a lower oxygen dose. The inverse relationship between oxygen content in the silicon film and oxygen dose is attributed to the redistribution of oxygen during implantation. In the oxygen dose range studied, the thickness and the breakdown voltage of the buried oxide layer increase with increasing oxygen dose. Higher postimplant annealing temperature improves the isolation properties of the buried oxide ...

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFETs have been fabricated in LPCVD polysilicon. A 5000-Å n+poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm2/V.s. The drain-to-source breakdown voltage exceeds -20 V.

Photoluminescence and microstructural properties of high‐temperature annealed buried oxide silicon‐on‐insulator

The defect properties of buried oxide silicon‐on‐insulator (SOI) formed by high dose O+ ion implantation and annealed in the temperature range of 1150–1300 °C were examined using photoluminescence (PL) spectroscopy and transmission electron microscopy. The intensity of radiative defect levels at 0.814 and 0.862 eV measured by PL at 4.2 K was observed to decrease with increasing post‐implantation annealing temperature. A direct correlation between the radiative defect band intensities and etch defect density in the top silicon layer was observed. The correlation between defect density and PL defect band intensity was further verified by cross‐sectional transmission electron microscopy of the top silicon. This letter demonstrates for the first time the correlation between PL defect properties and microstructure of buried oxide SOI. From comparisons with radiative defect centers in oxygen precipitated and plastically deformed silicon, the radiative defect states in SOI silicon are shown to result from residu...

IIB-1 1.25-µm buried-oxide SOI/CMOS process for 16K/64K SRAMS

An InGaAs gate GaAs semiconductor-insulator-semicondt <:tor (SIS) FET with a controllable threshold voltage making use o the work function difference between the InGaAs gate and the CstAs channel-forming layer materials was fabricated for the first t ine. The GaAs SIS FET reported by us [l], [2] in 1984 had all! 11’GaAs layer as the gate, an undoped GaAlAs layer as the insuhtor, an undoped GaAs layer as the channel-forming layer, and hac the self-aligned source and drain n+-regions. The GaAs SIS FET is a GaAs version of a poly-Si gate Si MOSFET. The threshold voltage of the GaAs SIS FET is determined predominantly by the work function difference between the gate material and the charnelforming layer material. In the previous work, since both materials were GaAs, the threshold voltage had a too small value (V,, = + 35 mV) and was fixed to that value. In the present work, howeve(, by controlling the indium (In) content of the InGaAs gate, the threshold voltage of the FET could be controlled at our will. The FET has a multilayer structure grown by MBE: an undhped LEC GaAj substrate/undoped GaAs (1.5 pm)/undoped Ga, .. Al, As (ZOO A , x = 0.4)/n+-InyGal -,As (Si-doped, X 10’s/m3, 200 A ) , n+-GaAs (Si-doped, 1 X lOI8/cm3, 4800 A ) . The iniium content was changed as y = 0.1, 0.15, and 0.2. The top n’-Cia’As and n+-InGaAs layers formed the gate electrode. The threshold voltage of the fabricated InGaAs gate GaAs !

IIB-8 SOI edge parasitics and their couplings

IS FET showed almost linear dependence on the In content: VII, = 0.096, 0.29, and 0.45 V for In contents of y = 0.1, 0.15, and 3.2, respectively. For the low In content of y = 0.1, a threshold vol :age of V,, = 0.096 V is almost equal to that of the work function tlifference of the Ino,lGao,9As gate and the GaAs channel forming l2yer materials. For the higher In contents, i.e., y = 0.15 and y = 3.2, however, the threshold voltages are larger than those expected :Irom the work function differences. This may be attributed to the depletion layer produced by the misfit dislocations at the InGaAs/GaAlAs interface owing to the high In content. The GaAs SIS FET with an InGaAs gate having all the good features of a SIS FET plus the feature of a controllable thres lold voltage is important for the GaAs large-scale integrated circui :s.

Identification and control of edge leakage in mesa-isolated SIMOX MOSFETs

growth rates decrease from 20 X lo-’ cmis to the saturation one (8 X when the undoped region width L increases from 1 pm to the infinite. Such results are, of course, very useful from a view point of device applications. X-ray analyzing SEM shows that no diffusion and/or no migrations of impurities from the doped into the undoped regions in the amorphous layers. Therefore, these phenomena could not be explained by the doping effect for the undoped regions by heating or snowplow effects. At a moment, we speculate that these phenomena were caused by the retardation of (1 11) facets formation at the boundary between the doped and undoped regions. As a preliminary experiment, we have fabricated MOSFET’s by using the undoped recrystallized region as n-channel region. The maximum field effect mobility was 160 cm2/V * s . Optimization of fabrication conditions is expected to produce yet better performances and is being carried out presently.

Effects of grain boundary passivation on the characteristics of p-channel MOSFETs in LPCVD polysilicon

Summary form only given. Separation by implantation of oxygen (SIMOX) into silicon to obtain silicon-on-insulator substrates has emerged as the leading technology for radiation-hard integrated circuits. A key issue in building CMOS devices on SIMOX substrates is the device leaking current, which in turn determines the standby current of circuits. One cause of high leakage current is metal impurities incorporated during the oxygen implant. A second mechanism for leakage current in mesa-isolated SIMOX transistors is identified here. This current, which occurs along mesa edges, is more detrimental to circuit performance. It is random, and the probability of its occurrence increases with an increase in the number of edges, shorter-channel transistors, and/or longer source-drain anneal cycles. Measurements suggest that the random edge leakage is caused by enhanced lateral diffusion of source-drain dopants along the mesa edges.<<ETX>>