H.W. Lam

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Method of fabricating display with semiconductor circuits on monolithic structure and flat panel display produced thereby

Method of fabricating a display with silicon integrated circuits included on the same monolithic structure and the flat panel display produced thereby. The display which may be of the liquid crystal or electrochromic type, for example, is formed as an x-y matrix display having individual address transistors respectively asociated with each of the display units or pixels. The substrate is preferably of transparent material, such as quartz or a glass plate, on which a polysilicon layer is disposed. The polysilicon layer is patterned to provide a plurality of islands which are subjected to a laser annealing treatment at an intensity sufficient to cause recrystallization thereof. The polysilicon material in the islands is converted by the laser annealing to crystalline silicon having an enhanced electron mobility characteristic such that a matrix array of address transistors in the form of MOSFETS can be fabricated in the individual islands. Thereafter, elements of the display are formed in conjunction with the matrix array of address transistors, beginning with the formation of an array of metal electrodes in respective association with corresponding address transistors. Various peripheral circuits for the display, such as drive circuits, are formed in other islands of crystalline silicon resulting from the laser annealing of the polysilicon islands such that a monolithic structure including a display with silicon integrated circuits for operating the display is produced.

Microstructure of high-temperature annealed buried oxide silicon-on-insulator

The microstructure of buried oxide silicon‐on‐insulator (SOI) annealed in the temperature range of 1150–1300 °C was examined. The microstructure of the buried oxide SOI was improved by increasing the annealing temperature. The minimum channeling yield of the top silicon layer in 1250 °C annealed SOI measured by Rutherford backscattering and channeling analysis is 5% which is comparable to unprocessed bulk single crystal material. This is further verified by the cross‐sectional transmission electron microscopy observation of the precipitate‐free top silicon layer with low dislocation density. The improvement in the microstructure is attributed to the dissolution of oxygen precipitates and oxygen outdiffusion during high‐temperature annealing.

Transient Radiation Effects in SOI Memories

This paper presents the first measurements of transient radiation effects on SOI discrete devices and an LSI memory. A commercially processed LSI SOI memory, a 4K × 1 SRAM on SIMOX, was tested for SEU, and transient ionizing radiation effects as a function of bias conditions and dose rate. The SEU error rate was found to be between 1.5 and 2.5 × 10-8 errors/bit-day for the 10% worst-case orbit model. The output voltage logic upset level was greater than 1.6 × 1010 rad(Si)/sec for Vcc supply voltage variations of -10% and +20% with Vsub at -10 V. For the discrete devices and memory, the measured transient photocurrents were larger than the calculated volumetric photocurrent generated in the active device region. This increased transient response is postulated to be due to the gain of the parasitic phototransistor of the dielectrically isolated MOS device.

Subgrain boundaries in laterally seeded silicon‐on‐oxide formed by graphite strip heater recrystallization

A detailed microstructural analysis of laterally seeded silicon‐on‐oxide formed by scanning graphite strip heater recrystallization is presented for the first time. The recrystallized top silicon layer has a (100) orientation, but contains many subgrain boundaries formed by dislocation coalescence. The subgrains are misoriented by <0.3° and have no internal defects. β‐SiC contamination of the top silicon layer was detected. It is probably due to particulate contamination from the top graphite strip heater.

Microstructural characterization of nitrogen‐implanted silicon‐on‐insulator

The effects of implant dose and postimplant annealing treatment on the microstructure of nitrogen‐implanted silicon‐on‐insulator were studied by cross‐sectional transmission electron microscopy techniques. In the lower dose case (0.75×1018/cm2) an amorphous silicon layer forms after implantation. Annealing at 1200 °C or higher results in a buried polycrystalline α‐Si3N4 layer containing many randomly oriented silicon particles. Higher dose implantation results in an amorphous silicon‐nitride layer. A porous layer also forms in the middle of the amorphous layer if the implant dose is 1.2×1018/cm2 or higher. The crystallization of the amorphous layer in the higher dose cases is shown to happen in two steps. In the first step nucleation and growth of α‐Si3N4 grains occur in the amorphous nitride region to form a spherulitic polycrystalline structure. The second step is the cellular growth of the spherulitic nitride grains into the crystalline silicon regions. Silicon particles are trapped at the cell walls a...

Characteristics and Three-Dimensional Integration of MOSFET's in Small-Grain LPCVD Polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Novel SOI CMOS design using ultra thin near intrinsic substrate

A novel SOI CMOS design has been explored. It utilizes an ultra thin near intrinsic substrate wherein no channel doping is introduced during processing. The enhancement operation is realized solely by proper adjustment of work function difference through p+ poly gate for n-channel devices and n+ poly gate for p-channel devices. The absence of depletion charge in this structure is conducive to improved drive current and threshold control. The structure has been realized by implanted buried oxide SOI technology.

Device fabrication in {100} silicon-on-oxide produced by a scanning CW-laser-induced lateral seeding technique

By using a CW-laser-beam-induced lateral seeding technique, which is a zone-melting crystal-growth process, single-crystal silicon-on-oxide with{100}orientation has been obtained. To adopt this process for silicon-on-insulator (SOI) MOS transistor fabrication, a masking level has been added to an exisiting n-MOSFET mask set so that a fully recessed oxide layer may be grown in selected regions of a silicon wafer; the exposed silicon region becomes the seed region. After depositing a 0.5-µm-thick layer of undoped low-pressure CVD polysilicon on the wafer, a laser process is performed to induce epitaxial growth in the polysilicon-on-silicon region, which in turn seeds the zone growth of the polysilicon-on-oxide region as the beam is traversed across the surface of the wafer. N-channel MOS transistors have been fabricated in the silicon-on-oxide material using projection printing lithography. Both complete-island-etch (CIE) and LOCOS techniques have been used for device-to-device and device-to-substrate isolation. Surface electron mobilities as high as 740 cm2/V . s, comparable to that obtainable in bulk-type devices, have been measured in 5-µm channel-length devices. It is shown that the back interface between the recrystallized silicon and the oxide layer is the dominant contributor to the subthreshold leakage current due to a combined effect of a high fixed oxide charge density and drain-induced barrier lowering. A high dose (\sim 10^{12}cm-2) deep boron implantation centered at the back interface and a back-gate bias have been shown to be effective in suppressing the leakage current to as low as 1-pA/µm channel width at VDS= 2 V, comparable to the best results obtained in silicon-on-sapphire (SOS).

The effects of oxygen dose on the formation of buried oxide silicon‐on‐insulator

The effects of the oxygen dose on the microstructure and the dielectric properties of the buried oxide in oxygen implanted silicon‐on‐insulator (SOI) structures have been studied. Cross‐sectional transmission electron microscopy analyses show that the density of oxygen precipitates at the silicon/buried‐oxide interface increases with a decreasing oxygen dose when identical annealing processes are employed. Annealing studies reveal that 1275 °C anneals annihilate the oxygen precipitates. A longer annealing time is required to achieve an oxygen‐precipitate‐free silicon layer in an SOI substrate implanted with a lower oxygen dose. The inverse relationship between oxygen content in the silicon film and oxygen dose is attributed to the redistribution of oxygen during implantation. In the oxygen dose range studied, the thickness and the breakdown voltage of the buried oxide layer increase with increasing oxygen dose. Higher postimplant annealing temperature improves the isolation properties of the buried oxide ...