C.H. Cho

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

A 512 Mb DRAM using a recessed channel array transistor with asymmetric channel doping scheme (RCAT-ASC) is fabricated for the first time with 80 nm feature size. We have found that RCAT-ASC shows much better device performance than the normal RCAT-SC (recessed channel array transistor with symmetric channel doping scheme) or PCAT-ASC (planar channel array transistor with asymmetric channel doping scheme). The RCAT-ASC has the lowest junction leakage currents at storage nodes among them. The increase of data retention time is found to be very remarkable, and thus we suggest that the RCAT-ASC should be an effective method for longer data retention time of DRAM for the future generations. Additionally, we also found that the charge sharing time (tCS) of RCAT-ASC has the lowest values among the three array transistor schemes.

Highly manufacturable 4 Gb DRAM using using 0.11 /spl mu/m DRAM technology

4 Gb DRAM has been developed successfully using 0.11 /spl mu/m DRAM technology. Considering manufacturability, we have focused on developing patterning technology that makes 0.11 /spl mu/m design rules possible using KrF lithography. Also, novel DRAM technologies, which have a big influence on the future DRAM integration, are developed as follows:, using novel oxide (SOG) for the enhanced capability of gap-filling, borderless metal contact and stud processes, line-type storage node SAC, thin gate oxide, and CVD Al process for metal interconnections.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

Novel DRAM cell transistor with asymmetric source and drain junction profiles improving data retention characteristics

A novel DRAM cell transistor with an asymmetric source and drain structure is proposed, for the first time, to realize reliable high density DRAM below 0.12 /spl mu/m. The new cell structure could provide the optimized source and drain junction profiles independently. The junction profile at the storage node (SN) was designed to reduce electric field to minimize junction leakage current and thereby improving data retention time. On the other hand, the junction profile at the bit-line direct contact node (DC) was designed to suppress short channel effects of a cell transistor. It is considered to be highly scalable for device scaling and to solve fine printing and precise alignment requirements. The validity of the approach was directly confirmed by improvement in the refresh times of 512 Mb DRAM which was fabricated with 0.12 /spl mu/m DRAM technology.

Highly manufacturable and high performance SDR/DDR 4 Gb DRAM

A 4 Gb SDR/DDR DRAM is fabricated with 0.11 /spl mu/m CMOS technology. To the best of our knowledge, this is the first working DRAM ever achieved at such a high density. The cell size and chip size of the 4 Gb DRAM are approximately 0.1 /spl mu/m/sup 2/ and 645 mm/sup 2/, respectively. The key technologies developed for this 4 Gb DRAM are KrF lithography with RET, novel ILD gap-filling, full SAC with LSC, novel W-BL, low-temperature Al/sub 2/O/sub 3/ MIS capacitor, and triple level CVD-Al interconnection technology. The key features of these technologies were reported elsewhere (Jeong et al., Tech. Digest of IEDM, pp. 353-6, 2000). The summary of 0.11 /spl mu/m DRAM technology is listed and compared with our previous 0.13 /spl mu/m (Kim et al., 2000) and 0.15 /spl mu/m (Kim et al., 1998) generations. We have found that random single-bit and/or twin-bit failures and block failures are the most critical issues to be solved for achieving good functionality of 4 Gb DRAM. In order to get rid of the single and twin bit failures, 80 nm array transistors, sub-80 nm memory cell contacts and mechanically robust capacitors are developed and triple-level CVD Al technology is optimized to reduce block failure as well as improve chip performance. In this paper, these technologies for achieving good functionality with high performance are highlighted in detail.

A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM

The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.

The influence of IMD bake process on buried channel PMOS hot carrier reliability of advanced DRAM

We investigated the influence of the SOG deposition with two kinds of curing process on the hot carrier reliability of buried channel (BC) PMOSFET. It was found that the vacuum bake induced the effective negative charges in the trench sidewall oxide and degraded P+ active isolation and PMOS hot carrier reliability.