D.I. Bae

A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI

A 10nm logic platform technology is presented for low power and high performance application with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrate. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limit. Multi-workfunction (WF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by channel dopants.

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

An 8 Gb multi-level NAND flash memory with 63 nm STI CMOS process technology

An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.

Improvement of data retention time in DRAM using recessed channel array transistors with asymmetric channel doping for 80 nm feature size and beyond

A 512 Mb DRAM using a recessed channel array transistor with asymmetric channel doping scheme (RCAT-ASC) is fabricated for the first time with 80 nm feature size. We have found that RCAT-ASC shows much better device performance than the normal RCAT-SC (recessed channel array transistor with symmetric channel doping scheme) or PCAT-ASC (planar channel array transistor with asymmetric channel doping scheme). The RCAT-ASC has the lowest junction leakage currents at storage nodes among them. The increase of data retention time is found to be very remarkable, and thus we suggest that the RCAT-ASC should be an effective method for longer data retention time of DRAM for the future generations. Additionally, we also found that the charge sharing time (tCS) of RCAT-ASC has the lowest values among the three array transistor schemes.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

Bottom oxidation through STI (BOTS) - A novel approach to fabricate dielectric isolated FinFETs on bulk substrates

We report a novel approach to enable the fabrication of dielectric isolated FinFETs on bulk substrates by bottom oxidation through STI (BOTS). BOTS FinFET transistors are manufactured with 42nm fin pitch and 80nm contacted gate pitch. Competitive device performances are achieved with effective drive currents of Ieff (N/P) = 621/453 μA/μm at Ioff = 10 nA/μm at VDD = 0.8 V. The BOTS process results in a sloped fin profile at the fin bottom (fin tail). By extending the gate vertically into the fin tail region, the parasitic short-channel effects due to this fin tail have been successfully suppressed. We further demonstrate the extension of the BOTS process to the fabrication of strained SiGe FinFETs and nanowires, providing a path for future CMOS technologies.

10nm FINFET technology for low power and high performance applications

In this paper, we present a 10nm CMOS platform technology for low power and high performance applications with the tightest contacted poly pitch (CPP) of 64nm and metallization pitch of 48nm ever reported in the FinFET technology on both bulk and SOI substrates. A 0.053um2 SRAM bit-cell is reported with a corresponding Static Noise Margin (SNM) of 140mV at 0.75V. Intensive multi-patterning technology and various self-aligned processes have been developed with 193i lithography to overcome optical patterning limits. Multi-workfunction (MWF) gate stack has been enabled to provide Vt tunability without the variability degradation induced by Random Dopant Fluctuation (RDF) from channel dopants.

Resistive switches in Ta 2 O 5-α /TaO 2−x Bilayer and Ta 2 O 5-α /TaO 2−x /TaO 2−y Tri-layer Structures

Enough R_off/R_on ratio is important for RRAM application. In this study, a Ta₂O_5-α/TaO_y/TaO_x tri-layer structure device was fabricated by reactive sputtering and plasma oxidation and a Ta₂O_5-α/TaO_x bi-layer structure device was also fabricated for comparison. Resistive switching characteristics of both types of devices were investigated under different compliance current. Both types of devices revealed nearly the same reset current which was as low as ~40 μA. The R_off/R_on ratio of the tri-layer structure devices was increased from 2 to more than 20 by inserting a TaO_y layer. The memory windows of the bi-layer structure devices increased to 3 while the memory windows of the tri-layer structure devices decreased to 8 when the compliance current increased from 40 μA to 60 μA. The stability of the tri-layer structure devices became worse under larger compliance current. The results indicate that that inserting a TaO_y is beneficial for the memory windows of devices and a smaller compliance current is more suitable for the tri-layer structure devices.

Improvement of data retention time using DRAM cell with metallic shield embedded (MSE)-STI for 90nm technology node and beyond

As the technology node of DRAM goes below 100 nm, the dimensional scaling of the devices greatly influences the major parameters that determine the performance of DRAM. Especially, the reduction of the isolation space in a cell array can deteriorate the characteristics of the cell transistor and storage node junction, which results in a degradation of data retention time. In order to overcome these issues, metallic shield embedded (MSE)-STI has been proposed but has not been realized yet. In this paper, for the first time, we successfully demonstrate a DRAM cell transistor with MSE-STI for the 90 nm DRAM technology node and beyond. As a result, we can obtain a reliable cell transistor with low-doped channel profile, uniform threshold voltage distribution and low junction leakage current, and most importantly,we can greatly improve data retention characteristics.