Radu Surdeanu

Evidence on the mechanism of boron deactivation in Ge-preamorphized ultrashallow junctions

We investigate the thermal stability of boron-doped junctions formed by Ge preamorphization and solid phase epitaxial regrowth. Isochronal annealing and characterization by sheet resistance, secondary-ion mass spectrometry, and spreading-resistance measurement are used to extract detailed information on the thermal stability of the boron activation. Using a previously established model of self-interstitial defect evolution from clusters to dislocation loops, we perform simulations of the release of interstitials from the end-of-range region. The simulations indicate that the measured deactivation is driven by interstitials emerging from the end-of-range defect region.

Leakage optimization of ultra-shallow junctions formed by solid phase epitaxial regrowth

Ultra-shallow p+ junctions formed by solid phase epitaxial regrowth (SPER) have promise for sub-65 nm CMOS technologies. Due to above-equilibrium solid solubilities and minimal diffusion, such junctions can far outperform spike-annealed junctions in terms of resistance, abruptness, and depth. However, the low-temperature annealing does not dissolve the end of range defects creating concerns for junction leakage in the device. In this work, we show how SPER junctions can be optimized to meet the ITRS junction profile and low-power leakage requirements of the 45 nm CMOS node [International Technology Roadmap for Semiconductors (Semiconductor Industry Association, San Jose, CA, 2001)]. Diode leakage is shown to decrease with Ge amorphization depth and B dose and energy. Leakage is shown to increase dramatically with the background doping level. Increasing the regrowth, or post-annealing, thermal budget improves leakage and can be optimized to avoid deactivation. The inclusion of a preanneal does not affect t...

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness ( 4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Chemical and electrical dopants profile evolution during solid phase epitaxial regrowth

Solid phase epitaxial regrowth (SPER) is a promising method for junction formation of sub-65 nm complementary metal–oxide–semiconductor technology nodes. This is mainly due to a high dopant activation level, easy control over electrical junction depth, excellent abruptness, and limited boron diffusion. In the present research we investigate in detail the activation process and the chemical profile change after SPER junction activation with respect to the regrowth temperature. We also obtain the electrically active profiles. We find that the process window for SPER between T=620 °C and T=740 °C offers the best activation level and has a dopant profile similar to the as-implanted. While increasing the regrowth temperature, we observe the gradual increase of the transient enhanced diffusion effect and formation of B trapping centers in the end-of-range (EOR) region. At temperatures as high as T=800 °C and T=850 °C the dopant activation beyond the original a-Si layer is observed and the high metastable B acti...

Optimizing p-type ultra-shallow junctions for the 65 nm CMOS technology node

The limits of using B or BF2 alone in forming ultrashallow junctions have been reached for the 90 nm CMOS generation. In this paper we evaluate the use of Ge and F co-implants to extend conventional implantation and spike anneal to the 65 nm CMOS technology node. In this work we show that the F co-implant can improve the abruptness of the B junction, while the single Ge usually degrades it. The use of Ge co-implanted with F gives the best junction abruptness - less than 5nm/decade. The best trade-off between junction depth (Xj) and sheet resistance (Rsheet) is achieved by deep Ge pre-amorphization and deep co-implantation of F. A comparison between slow and fast ramp-up is made. Significant improvement for the junction activation, its depth and abruptness is obtained by spike anneal with fast ramp-up for B junctions with Ge and F co-implantation.

Minimization of the MuGFET contact resistance by integration of NiSi contacts on epitaxially raised source/drain regions

High parasitic S/D resistance is a major obstacle in realizing future generations of CMOS technologies using multiple gate devices with narrow fins. This makes selective epitaxial growth of Si in the S/D regions, the enabling process for multiple gate CMOS technologies. In this paper, we endeavor to integrate a low temperature selective epitaxial growth process and a low temperature NiSi process to form low resistance S/D contacts. Our experimental results show 34% and 11% improvement in parasitic S/D resistance of N-and P-channel multiple gate FETs with less than 20 nm wide fins respectively.

SPER junction optimisation in 45 nm CMOS devices

Ultra-shallow junction formation by solid phase epitaxial regrowth (SPER) has been shown to produce excellent junction profiles beyond that of conventional spike annealing. However residual damage can degrade various aspects of the transistor performance, annihilating any:improvement due to the junction profile. In this work we look at optimizing the junction and channel conditions to meet the dopant profile and transistor requirements for the 45 nm CMOS node. We show how an optimised junction implant and low temperature SPER spike anneal can further increase the activation level and profile of the junction. In devices we show results on the effect of SPER processing on both the substrate and gate doping. This includes junction overlap, channel deactivation, contact resistance, junction leakage, poly depletion, and gate leakage. We address each of these concerns for both pMOS and nMOS and identify what are the main strengths and weaknesses of SPER in devices.

Channel engineering and junction overlap issues for ultra-shallow junctions formed by SPER in the 45 nm CMOS technology node

The feasibility of the SPER junction process as a reasonable alternative to the spike anneal junction is proved in this work. Good control of the SCE and performance competitive results as compared to the spike junction are obtained. An analysis of the interaction between the halo dopant and the SPER junctions has been carried out; it is shown that the performance degrades with increasing halo dose as a consequence of an overlap resistance problem.

Advanced PMOS Device Architecture for Highly-Doped Ultra-Shallow Junctions

In this paper we study the integration of Boron ultra-shallow junctions (USJ) obtained by Germanium pre-amorphization, Fluorine co-implantation and fast ramp-up and ramp-down anneals into advanced p-channel metal-oxide-semiconductor (PMOS) devices. Several integration issues associated to these USJ are investigated: short-channel effects control, implantation tilt angle influence, junction de-activation, thermal budget, silicide process. We show that remarkable PMOS device performance enhancement (Ion=450 µA/µm at Ioff=250 nA/µm for devices with Lg\cong50 nm) can be achieved when full potential of highly-active and abrupt USJ is exploited by combining it with a low thermal budget integration scheme and a low contact resistance NiSi.

Pre-amorphization and co-implantation suitability for advanced PMOS devices integration

now at Philips Semiconductors, Crolles, France