Nisha Checka

Technology, performance, and computer-aided design of three-dimensional integrated circuits

We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

FDSOI Process Technology for Subthreshold-Operation Ultralow-Power Electronics

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.

Passive acoustic sensing for tracking knocks atop large interactive displays

Describes a system that locates the position of knocks and taps atop a large sheet of glass. Our current setup uses four contact piezoelectric pickups located near the sheets corners to record the acoustic wavefront coming from the impacts. A digital signal processor extracts relevant characteristics from these signals, such as amplitudes, frequency components, and differential timings, which are used to estimate the location of the hit and provide other parameters, including the rough position resolution, the nature of each hit (e.g., knuckle knock, metal tap, or fist bang), and the strike intensity. As this system requires only simple hardware, it needs no special adaptation of the glass pane, and allows all transducers to be mounted on the inner surface, hence it is quite easy to deploy as a retrofit to existing windows. This opens many applications, such as an interactive storefront, with content controlled by knocks on the display window.

The effect of substrate noise on VCO performance

This study characterizes the effect of substrate noise on a standard component of the RF front end: the voltage controlled oscillator (VCO), as well as evaluating the effect of VCO bias current and guard rings on noise performance. Frequency effects of substrate noise are also examined through the study of VCOs at three different center frequencies: 900 MHz, 2.4 GHz, and 5.2 GHz. Substrate noise is a serious problem that continues to plague mixed-signal designs. Components of the RF frontend are particularly sensitive to substrate noise as the effectiveness of standard isolation techniques degrades at higher frequencies. This study has shown that the phase noise of a VCO is adversely affected by substrate noise. In the extreme, the VCO can lock to the substrate noise. Guard rings can effectively attenuate substrate noise at lower frequencies. For example, at 900 MHz, as much as 25 dB of isolation is observed. At 5.2 GHz, the isolation reduces to 10 dB. Furthermore, the use of guard rings can improve the response of the VCO to injection locking.

Passive acoustic knock tracking for interactive windows

We describe a novel interface that locates and characterizes knocks and taps atop a large glass window. Our current setup uses four contact piezoelectric pickups located near the sheets corners to record the acoustic wavefront coming from the knocks. A digital signal processor extracts relevent characteristics from these signals, such as amplitudes, frequency components and differential timings, which are used to estimate the location of the hit and provide other parameters, including the rough accuracy of this estimate, the nature of each hit (e.g., knuckle knock, metal tap, or fist bang), and the strike intensity. This system requires only simple hardware, needs no special adaptation of the glass pane, and allows all transducers to be mounted on the inner surface, hence it is quite easy to deploy as a retrofit to existing windows. This opens many applications, such as an interactive storefront, with projected content controlled by knocks on the display window.

Characterization of a three-dimensional SOI integrated-circuit technology

This paper describe the process and test results after single tier circuit fabrication as well as after three-tier integration, determine impact of 3D vias on ring oscillator performance, and demonstrate functionality of single and multi-tier circuits of varying complexity.

Substrate noise analysis and experimental verification for the efficient noise prediction of a digital PLL

Substrate noise is a major impediment to mixed-signal integration. This paper describes a CAD tool that can be used at any stage of the design cycle to estimate the substrate noise generated by large digital circuits. The results have been verified with substrate noise measurements on a 480 MHz digital PLL implemented in a 90 nm CMOS process on a high resistivity substrate.

Circuit Architectures for 3D Integration

The recent electronics revolution has been fueled by the decades-long trend of exponential growth in circuit performance through device scaling. In current and future technologies, simple device scaling does not result in the same performance improvements. For deeply scaled technologies, optimizing interconnect performance is of equal importance as device performance. Following the International Technology Roadmap for Semiconductors (ITRS) specifications for scaled interconnect, worst-case and even average-case interconnect performance decreases with each technology generation [11]. Because the performance improvement achievable through Moore’s law scaling is bottoming out, new technologies to achieve performance enhancement are being explored. Three-dimensional integration is one such technology. Three-dimensional integration offers several performance improvements for electronic systems. First, 3D integration offers a greater device density for a given footprint area. Essentially, more functionality can be packed into a given area. Second, long, global wires can be replaced with shorter, local wires by exploiting vertical interconnect used to connect device layers. This results in lower power dissipation and shorter timing delays. Finally, a 3D technology permits the integration of heterogeneous technologies. Using a wafer-bonding approach to 3D integration, each device layer is fabricated independently of every other device layer allowing each system to be fabricated in a different technology. Circuits that are part of system-on-a-chip (SOC) applications can be fabricated in the device technology that yields optimal performance and then subsequently integrated together using a 3D integrated technology. Because each subsystem is fabricated in the optimal technology, optimal overall system performance can be achieved. The implication of each benefit of 3D integration on circuit architectures is the subject of this chapter. Section 13.2 describes SOC applications. Section 13.3