Khaled Ben Ali

RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate

RF performance of a 200-mm commercial-enhanced signal integrity high resistivity silicon-on-insulator (eSI HR-SOI) substrate is investigated and compared with its counterpart HR-SOI wafer. By measuring coplanar waveguide lines and substrate crosstalk structures, it is demonstrated that losses are completely suppressed leading to virtually lossless linear substrate. Moreover, a reduction of the second harmonic distortion by more than 25 dB is measured on eSI HR-SOI wafer compared with HR-SOI. Excellent matching between experimental dc and RF characteristics of fully depleted SOI MOSFETs measured on top of HR-SOI and eSI HR-SOI is demonstrated. Furthermore, digital substrate noise is reduced by more than 25 dB on eSI HR-SOI compared with HR-SOI, when injected noise varies from 500 kHz to 50 MHz. The eSI HR-SOI substrate is fully compatible with the CMOS process and could be considered as a promising solution for the RF front-end-modules integration and system-on-chip applications.

RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

In this paper we aim at comparing the static and RF performances of passive and active fully-depleted (FD) SOI MOSFETs fabricated on top of either a standard or a trap-rich HR-SOI UNIBOND wafer both provided by SOITEC.

RF non-linearities from Si-based substrates

In this paper, RF performance and non-linearity analysis of different silicon substrates including standard, porous, high-resistivity (HR) and trap-rich HR types (TR) are explored experimentally and by simulation. The investigation is done by means of coplanar transmission lines (CPW) fabricated on these substrates. It is demonstrated that TR-Si characteristics in terms of high resistivity, attenuation and linearity are effectively enhanced.

Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates

Substrate crosstalk and RF losses in HR-SOI, and the introduction of a stabilized polysilicon layer are deeply investigated. A new equivalent lumped circuit to model different substrate types and resistivities, and SiO2-Si interface qualities is proposed and validated by simulation and experimental data. It is also valid to model the introduction of high-trap density at the interface, and it successfully explains the higher measured values of substrate crosstalk at low frequencies for HR-Si substrates.

RF and non-linearity characterization of porous silicon layer for RF-ICs

Nanostructured porous silicon is very promising for RF applications by overcoming the high-frequency losses originating from the bulk silicon substrate. RF performance and non-linearity analysis of different silicon substrates including, porous (PSi), trap-rich (TR) high resistivity (HR) types are explored experimentally. The investigation is done by means of coplanar transmission lines (CPW) fabricated on these substrates. RF measurements of transmission lines demonstrate the successful reduction of the permittivity and increase of the resistivity of the PSi substrate. It also demonstrated that the insertion losses and linearity are efficiently enhanced.

Photo-Induced Coplanar Waveguide RF Switch and Optical Crosstalk on High-Resistivity Silicon Trap-Rich Passivated Substrate

A continuous-wave mode optically controlled coplanar waveguide radio frequency (RF) switch on high-resistivity silicon substrate with and without trap-rich polysilicon (poly-Si) layer is investigated. Because of the local poly-Si trap-rich layer, we experimentally show the important reduction of optical crosstalk without degrading the photo-controlled RF switch performance. A photo-induced plasma confinement by locally etching the poly-Si layer to control the photogenerated free carriers and their lateral diffusion is realized. Optical crosstalk between two coplanar waveguide RF switches is reduced by at 20 GHz.