Chan-Yen Chou

Design, analysis, and development of novel three-dimensional stacking WLCSP

A robust and rapid development procedure for a novel three-dimensional stacking wafer level chip-scaled packaging (3DS-WLCSP), emphasizing the finite-element parametric analysis and experimental validation, is disclosed herein. This design procedure is comprised of the fundamental validation of conventional wafer-level chip-scaled packaging (WLCSP), design methodology development of the test vehicles and then the fabrication of the proposed 3DS-WLCSP structure. Based on the validation of the conventional WLCSP measurement and experiment, a reliable finite-element model can be achieved. However, in order to reduce the product design period, a simplified Glass-WLCSP is chosen as the test vehicle in the parametric design/validation procedure. Through the parametric analysis, one can obtain robust design parameters. Therefore, the proposed 3DS-WLCSP can be fabricated within the validated design parameters.

Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Accompanying the popularization of portable and handheld products, high reliability under board level drop test is a great concern to semiconductor manufacturers. In this study, a stress-buffer-enhanced package with fan-out capability is proposed to meet the high requirement of drop test performance. Both drop test experiment and numerical simulation were performed. The results showed the first failure of proposed package passed over 100 drops (mean-life-to-failure over 240 drops). Moreover, the failure of broken trace metal in the stress-buffer-enhanced package which is different from the solder joint failure in the conventional wafer level package was observed both in experiments and dynamic simulations. Simulation results were validated with experimental data and explained how the proposed stress-buffer-enhanced package improved drop test performance.

Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis

The stress buffer layer (SBL) is a widely applied improvement in many advanced packages used to release the stress concentration at solder joints. However, it has been generally found that the metal line adjacent to the SBL may suffer larger deformation and its reliability should be addressed. In this study, the panel level package (PLP) technology with solder on polymer (SOP) structure is selected as the testing sample to investigate the effect of SBL. The ball shear strength test is conducted first to investigate the reliability of metal trace in PLP. In addition, finite element (FE) analysis is applied to understand the actual thermo-mechanical behavior of PLP after its assembly. The package-level and board-level reliability assessments are compared, and the suggested layout of the redistribution layer on the SBL is provided herein.

The solder on rubber (SOR) interconnection design and its reliability assessment based on shear strength test and finite element analysis

A novel chip-on-metal structure of the advanced wafer level chip scale package (WLCSP) which has the capability of redistributing the electrical circuit is proposed in this study. In the WLCSP, the solder on rubber (SOR) design expands the chip area and also provides a buffer layer for the deformation energy from the coefficient of thermal expansion (CTE) mismatch. By using the solder ball shear test, the stress/strain-released behavior in the SOR structure is investigated in this research. On the other hand, a three-dimensional nonlinear finite element (FE) model for the ball shear test is established to assist the design of the package. The force-displacement curves from the FE analysis are compared with the experimental results to demonstrate the accuracy of the simulation. Likewise, the issue from element mesh density is also discussed herein. The investigation reveals that the SOR structure could highly decrease the damage in solder bumps from the ball shear test. Furthermore, the transferred stress/strain in the interconnect near the contact pad could be diminished through a suitable layout of redistribution lines.

Mechanical characteristic of ssDNA∕dsDNA molecule under external loading

The elasticity and extensibility behaviors of sequence-dependent single stranded and double stranded DNA (ssDNA∕dsDNA) under various external loading conditions are studied by the clustered atomistic-continuum mechanics (CACM). The proposed numerical CACM is based on the finite element method, and it comprises both the atomistic-continuum and clustered atomistic-continuum (the clustered atoms are treated as a single super atom) mechanics. Through the CACM simulation, the transient mechanical response of the DNA could be revealed, including the stretching and rotating of the DNA backbone. Moreover, good agreement was achieved between the numerical simulation and single molecule experimental results.

Prediction of the bulk elastic constant of metals using atomic-level single-lattice analytical method

An atomic-level single-lattice method with a closed-form equation is presented to predict the elastic characteristics of bulk metals. In this letter, the interatomic forces of single body-centered-cubic (bcc) and face-centered-cubic (fcc) lattices are described as atomic springs, the single bcc and fcc lattices are therefore constructed as simple spring network models. The analytical result indicates that the calculated single-lattice elastic characteristics and the experimental bulk values are within a reasonable range. This analytical equation also provides a feasible way of taking a second look at the Morse potential coefficients of metallic atoms.

Investigation of stress-buffer-enhanced package subjected to board-level drop test

In this research, the objective is to develop a stress-buffer-enhanced package subjected to board level drop test under a high-G impact drop; both drop test experiments and ANSYS/LS-DYNA simulations are executed. Many researchers indicate that solder joints in wafer level chip scale package (WLCSP) are the weakest portion in board-level drop test because of the large relative motion between the board and the chip mounted on it and the brittle intermetallic compound (IMC) layer. To compare with the failure mechanism of traditional WLCSP structure, the stress-buffer-enhanced package shifts its failure mode to the trace damage on the chip side. Because the soft stress buffer layer has relatively larger elongation to reduce the impact to the solder joints, the corner between the solder joints and connection trace becomes the critical region which may break due to the stress concentration effect. In the drop test experiment, the proposed stress-buffer-enhanced package passed over 100 drops (most packages passed 240 drops); the performance far exceeds the JEDEC criterion which is 30 drops. Following, three phases of drop test simulation are conducted to elucidate the mechanical behavior of board and packages during the blink of impact. Results show that the stress at proposed stress-buffer-enhanced package is much smaller than that at conventional WLCSP. On the other hand, the trace stress level of proposed stress-buffer-enhanced package is slightly larger than that of conventional WLCSP. Simulation results explain the impact loading absorption of thick dielectric layer to reduce the stress level of solder joints.

Thermal Management on Hot Spot Elimination / Junction Temperature Reduction for High Power Density System in Package Structure

In this paper, a thermal enhanced design for a high power density system in package (SiP) is proposed to resolve the challenge faced by the packaging research community in eliminating the hot spot and reducing the junction temperature in a high operation temperature. The SiP structure includes seven sub-chips which are attached to the chip carrier. The dissipated heat is conducted to the metal slug by thermal vias, while some heat is conducted to the pads by metal traces. Finally, the whole module is connected to the test board by solder paste material. In the thermal enhanced design, a highly conductive material such as solder paste is applied to make an attachment between the chip carrier and the highest power density chip (the power amplifier chip). Besides, some thermal vias are constructed to conduct the dissipated heat from the chip carrier to the metal slug. The new structure greatly improves the thermal performance of the SiP structure. Moreover, the hot spot on the chip carrier is also eliminated in this thermal enhanced SiP structure.Copyright

Thermal design and transient analysis of insulated gate bipolar transistors of power module

Insulated gate bipolar transistors (IGBT) have been utilized in high power and fast switching applications for power management. Research on transient thermal performance assessment has become imperative because of the excessive heat generated from the IGBT chip. In this study, the transient thermal performance of the power chip under the power cycling test was investigated, and the temperature history on the chip was recorded by an infrared thermometer during the test. The test conditions of the experiment were based on: the International Electrotechnical Commission (IEC) standard. The current density distribution of the IGBT chip was investigated by electro-thermal finite element (FE) analysis. In order to validate the methodology for FE analysis, the predicted temperature distribution was compared with the experimental data under the same electrical load. Furthermore, the temperature-dependent material property was employed in electro-thermal FE analysis. The results show that the current crowding effect occurred near the periphery of the bonding wires. Moreover, the solder under the chip provided a significant route of heat dissipation in the power chip, when high power was applied.

Development of Empirical Equations for Metal Trace Failure Prediction of Wafer Level Package Under Board Level Drop Test

Accompanying the increasing popularity of portable and handheld products, high reliability for board level drop test becomes a great concern for semiconductor and electronic product manufacturers. Meanwhile, for design purpose, a reliable impact life prediction model is also a must in estimating the performance of packages subjected to drop impact. In this study, a stress-buffer-enhanced package is proposed to meet the high drop test performance requirement. Both the drop test experiment and numerical simulation were performed. The experimental drop test results showed that a different failure mode, the broken metal trace at package side, was observed in the stress-buffer-enhanced package. Several drop test simulations were conducted to elucidate the mechanical behavior of the test board and packages during the blink of impact. Based on the simulation results, a metal trace impact life prediction model is then developed for the novel stress-buffer-enhanced package to forecast the number of drops. Unlike the thermal cycle test, the dynamic response of the drop impact is irregular and not cyclic. As such, the concept of cumulative damage is considered in the life prediction model. Several characteristics of the metal trace dynamic response, the cumulative fatigue life, the cumulative plastic strain, and the cumulative effective plastic deformation, were studied during the development of the life prediction model. The results showed that the cumulative plastic strain of the metal trace could accurately predict impact life.