Chang-bong Oh

Thermal stability of atomic-layer-deposited HfO2 thin films on the SiNx-passivated Si substrate

HfO2 thin films were deposited on SiNx-passivated Si wafers at 300 and 400 °C using an atomic-layer-deposition technique. The SiNx films were deposited by another atomic-layer-deposition process at 595 °C. The SiNx films worked well as barriers to both Si and O diffusion, resulting in a small decrease in the capacitance density even after post-annealing at temperatures up to 1000 °C, compared either to the HfO2 film deposited directly on Si or an Al2O3-barrier-layer/Si substrate. The decrease in the capacitance density after post-annealing, although relatively small, was due to Hf and O diffusion into the interface layer. Interestingly, post-annealing under an atmosphere containing small amount of oxygen (∼1%) decreased the capacitance density to a smaller degree. However, the interface and bulk capturing of the carrier was serious, resulting in a rather large hysteresis (∼100 mV) voltage in the capacitance–voltage measurements even after post-annealing.

Improved current performance of CMOSFETs with nitrogen incorporated HfO 2 -Al 2 O 3 laminate gate dielectric

For the first time, we integrated poly-Si gate CMOSFETs with nitrogen incorporated HfO/sub 2/-Al/sub 2/O/sub 3/ laminate (HfAlON) as gate dielectrics. Both low gate leakage currents (0.1 mA/cm/sup 2/ at V/sub g/=+1.0 V) and low EOT (15.6 /spl Aring/) sufficiently satisfy the specifications (EOT=12/spl sim/20 /spl Aring/, J/sub g/=2.2 mA/cm/sup 2/) estimated by ITRS for low power applications. By in-situ 3 step post-deposition annealing, approximately 17 at.% nitrogen is incorporated at the HfAlON/Si interface. In-situ 3 step post-deposition annealing decreases metallic Hf bonding, which exists at the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate/Si interface. As a result, we can suppress C-V hysteresis and improve current performance. Finally, well-behaved 100 nm CMOSFET devices are achieved. The measured saturation currents at 1.2 V V/sub dd/ are 585 /spl mu//spl Aring///spl mu/m (I/sub off/= 10 nA//spl mu/m) for nMOSFET and 265 /spl mu/A//spl mu/m (I/sub off/=10 nA//spl mu/m) for pMOSFET, which are approximately 80% of those of nitrided SiO/sub 2/. In terms of I/sub on/-I/sub off/ characteristics of n/pMOSFETs, these results represent the best current performance compared with previous reports for poly-Si gate CMOSFETs with high-k gate dielectrics.

The effect of body contact arrangement on thin SOI MOSFET characteristics

Abstract Several body contact arrangement types have been studied to improve the parasitic phenomena such as the edge transistor effect and the bipolar action. The H-gate SOI MOSFET with the body contacts at both ends of channel was found to be most effective to suppress the edge transistor effect and reduce the drain leakage current and the bipolar action.

Fully working 1.10 /spl mu/m/sup 2/ embedded 6T-SRAM technology with high-k gate dielectric device for ultra low power applications

Ultra low power 1.10 /spl mu/m/sup 2/ 6T-SRAM chip with HfO/sub 2/-Al/sub 2/O/sub 3/ gate dielectric was for the first time successfully demonstrated for the system-on-chip applications. By carefully optimizing gate pre-doping process, gate leakage current was dramatically suppressed and poly deletion was reduced. Device performance was improved by 15% and 12% for NFET and PFET, respectively. The threshold voltage of long channel transistor was well controlled to the acceptable value (0.4V) by channel engineering. Equivalent oxide thickness of HfO/sub 2/-Al/sub 2/O/sub 3/ film was 17/spl Aring/ and gate leakage current density was 1600-times lower than that of the oxynitride. Current performance of 90nm gate length NFET and PFET with HfO/sub 2/-Al/sub 2/O/sub 3/ were 335 and 115 /spl mu/A/ /spl mu/m, while Ioff were 0.9 and 2.0pA/ /spl mu/m, respectively. SNM value of 1.10 /spl mu/m/sup 2/ 6T-SRAM bit cell was 340mV at Vdd = 1.2V. Stand-by current of the SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ was decreased by 2 orders, while access time was 1.65 times larger compared with that of SRAM chips with oxynitride at Vdd = 1.2V.

Highly stable SOI technology to suppress floating body effect for high performance CMOS device

High performance microprocessors with high stabilities are fabricated on Si and SiGe inserted (SGI) SOI wafers. The operation margins of voltages and frequency are characterized. For body floating devices, the operation margins at high Vdd and low frequency are narrow due to the floating body effect (FBE). These operation limits are drastically improved by applying a body contact for only NMOS at the critical circuits sensitive to the FBE. The maximum operation voltage increases from 1.8 V up to 2.5 V. The minimum operation frequency is lowered from 370 MHz to 220 MHz. The functionality of the NMOS body contact SOI microprocessor is comparable to that of the bulk. To maximize the SOI performance gain, body contacted and floating SOI devices should be optimized, and the smaller portion of body contacted devices are conclusive. For body floating SOI devices, the SGI SOI technology is very effective in suppressing SOI FBE and provides stable circuit operation.

Ultra low power 6T-SRAM chip with improved transistor performance and reliability by HfO/sub 2/-Al/sub 2/O/sub 3/ high-K gate dielectric process optimization

Ultra low power CMOS 6T-SRAM chips with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate gate dielectric were successfully demonstrated (bit-cell size=2.14 /spl mu/m/sup 2/). Equivalent oxide thickness (EOT) of 1.56 nm, the thin high-k gate dielectric NMOS and PMOS transistor had 470 and 150 /spl mu/A//spl mu/m at Ioff=0.1 nA//spl mu/m and Vdd=1.2 V, respectively. By deliberate optimizing the conditions of post nitridation and post deposition annealing (PDA) such as O/sub 2/ and N/sub 2/ PDA temperature, 60 and 82% of NMOS and PMOS mobility, respectively, compared to those of oxynitride were achieved without increasing EOT. And also, reliabilities of TDDB and HCI, and flicker noise characteristics of the thin high-k transistors were improved. For the 6T-SRAM with optimized thin high-k gate dielectric, static noise margin (SNM), cell delay, and chip yield were comparable to those of the oxynitride device while dynamic power was more than 2 orders lower (Vdd=1.0/spl sim/1.2 V).

Cost-effective process integration for a high performance 0.5 /spl mu/m CMOS logic device

A high performance and cost-effective process for a 0.5 /spl mu/m CMOS logic device optimized for 3.3 V has been developed. To fill contacts and via holes, an in-situ Al reflow technique was employed instead of the high cost W-plug process. It was found that the in-situ Al reflow technique was very effective in improving the electrical properties and reliabilities of the multilevel interconnects. Quasi-global inter-metal-dielectric (IMD) planarization has been achieved by the COmbining PHOtoresist etchback and SOG etchback (COPHOS) process.

Series resistance at metal contact for thin film SOI MOSFET

Thin-film silicon-on-insulator (TFSOI) MOSFET has emerged as a strong candidate for high performance, high density and latch-up free CMOS devices with less fabrication steps. Thin silicon film should be used to achieve good behavior in SOI MOSFET. However, most of the papers on TFSOI have reported high parasitic source/drain series resistance and contact resistance, which tends to obscure the performance advantages of SOI. In this paper, we examined effects of top silicon film thickness (Tsi) on contact series resistance and contact hole etching method.