Chang-Lee Chen

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

VA-2 New MBE buffer used to eliminate backgating in GaAs MESFET's

A new buffer layer bas been developed that eliminates backgating between MESFETs fabricated in active layers grown upon it. The new buffer is grown by molecular beam epitaxy (MBE) at low substrate temperatures (150-300°C) using Ga and As, beam fluxes. It is highly resistive, optically inactive, and crystalline, and high-quality GaAs active layers can be grown on top of the new buffer. MESFETs fabricated in active layers grown on top of this new buffer show improved output resistance and breakdown voltages; the dc and RF Characteristics are otherwise comparable to MESFETs fabricated by alternative means and with other buffer layers.

High-power-density GaAs MISFETs with a low-temperature-grown epitaxial layer as the insulator

A GaAs layer grown by molecular beam epitaxy at 200 degrees C is used as the gate insulator for GaAs MISFETs. The gate reverse breakdown and forward turn-on voltages, are improved substantially by using the high-resistivity GaAs layer between the gate metal and the conducting channel. It is shown that a reverse bias of 42 V or forward bias of 9,3 V is needed to reach a gate current of 1 mA/mm of gate width. A MISFET having a gate of 1.5*600 mu m delivers an output power of 940 mW (1.57-W/mm power density) with 4.4-dB gain and 27.3% power added efficiency at 1.1 GHz. This is the highest power density reported for GaAs-based FETs.<<ETX>>

High-breakdown-voltage MESFET with a low-temperature-grown GaAs passivation layer and overlapping gate structure

GaAs MESFETs were fabricated using a low-temperature-grown (LTG) high-resistivity GaAs layer to passivate the doped channel between the gate and source and between the gate and the drain. The gate was fabricated such that the source and drain edges of the metal gate overlapped the LTG GaAs passivation layer. The electric fields at the edges of the gate were reduced by this special combination of LTG GaAs passivation and gate geometry, resulting in a gate-drain breakdown voltage of 42 V. This value is over 60% higher than that of similar MESFETs fabricated without the gate overlap.<<ETX>>

High-Quality 150 mm InP-to-Silicon Epitaxial Transfer for Silicon Photonic Integrated Circuits

The integration of dissimilar materials is of great interest to enable silicon photonics and enable optical interconnects in future microprocessors. The wavelength transparency of Si in the telecom window 1.3–1.6 m is another compelling reason to integrate microphotonics and microelectronics. A major challenge for this integration is the incompatibility of the III–V compound and Si semiconductors used to implement microphotonics and microelectronics, respectively. Si and InP have an 8.1% lattice mismatch, making heteroepitaxial growth of InGaAsP compounds on Si with low misfit dislocation density difficult. 1

Reduction of sidegating in GaAs analog and digital circuits using a new buffer layer

Sidegating effects relevant to GaAs digital, analog, and monolithic microwave integrated circuits have been significantly reduced or eliminated by using a low-temperature buffer layer grown by molecular-beam epitaxy. At radio frequencies the low-temperature buffer layer reduced the signal coupling between devices, which is an important consideration in microwave integrated circuits. For digital circuit applications, the low-temperature buffer layer eliminated the dependence of the voltage level of an inverter on the logic state of adjacent devices and on the duty cycle of a pulse train encountered in the circuit. The highly resistive nature of the low-temperature buffer allows experimental identification of the role that a buffer layer plays in sidegating. >

Breakdown of overlapping-gate GaAs MESFETs

Gate-breakdown mechanisms in GaAs MESFETs have been studied by numerical simulation. The devices simulated include normal passivated and unpassivated MESFETs as well as overlapping-gate MESFETs passivated with low-temperature-grown (LTG) GaAs, normal GaAs, and silicon dioxide. The breakdown voltage is the highest for the overlapping-gate MESFET with LTG GaAs passivation, which agrees with the experimental results reported previously. The high breakdown voltage is the result of an altered electric field near the drain-edge of the Schottky-contact gate. This field modification is achieved most effectively by using an overlapping gate structure. The LTG GaAs is the best passivation layer because of its high resistivity and breakdown-field strength.

Sidegating reduction for GaAs integrated circuits by using a new buffer layer

Side-gating effects relevant to GaAs digital, analog, and monolithic microwave integrated circuits have been significantly reduced or eliminated by using a high-resistivity GaAs buffer layer grown at low substrate temperatures by molecular beam epitaxy (MBE). The high resistivity of the low-temperature (LT) GaAs buffer is attributed to an arsenic excess of approximately 1 at.%. For analog ICs operating at intermediate frequencies, the LT GaAs buffer eliminates the resistive component of RF coupling. The higher the frequency, the smaller the improvement in performance afforded by the LT GaAs buffer, because capacitive coupling increasingly dominates resistive coupling. The dependence of drain current on the duty cycle of an adjacent digital signal is also eliminated by using the LT GaAs buffer. At microwave frequencies, the LT GaAs eliminates the variation of MESFET equivalent circuit parameters with side-gate bias. Thus the restrictions on device and circuit layout currently imposed by side-gating can be eliminated.<<ETX>>

Transconductance compression in submicrometer GaAs MESFET's

The transconductance compression phenomenon in GaAs MESFETs is known to depend on the gate metal, processing, and the gate length. This phenomenon is thought to be caused by the depletion region under the free surface between gate and drain. Based on this assumption, a new model is proposed which is able to explain the experimental results for 0.25-µm gate-length devices satisfactorily.

150 mm InP-to-Silicon Direct Wafer Bonding for Silicon Photonic Integrated Circuits

A low-temperature direct wafer bonding process was developed to realize the high-quality transfer of the largest (150 mm in diameter) available InP-based epitaxial structure onto the prepatterned silicon-on-insulator (SOI) substrate. Over 95% bonding yield and a void free bonding interface was obtained. A InGaAsP multiple quantum-well (MQW) diode laser structure is well preserved after bonding, as indicated by the high-resolution X-ray diffraction (XRD) rocking curve measurement. XRD omega scans of the bonded wafers over a 9×9 matrix revealed a small bowing of only 64.12 µm, showing that the III-V epitaxial surface is relatively flat with low-strain. The first InGaAsP-based MQW hybrid Si evanescent racetrack ring lasers have been realized, showing comparable performance as previously InAlGaAs ring lasers.