Donna-Ruth W. Yost

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

High-speed Schottky-barrier pMOSFET with f/sub T/=280 GHz

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

3D integrated superconducting qubits

As the field of quantum computing advances from the few-qubit stage to larger-scale processors, qubit addressability and extensibility will necessitate the use of 3D integration and packaging. While 3D integration is well-developed for commercial electronics, relatively little work has been performed to determine its compatibility with high-coherence solid-state qubits. Of particular concern, qubit coherence times can be suppressed by the requisite processing steps and close proximity of another chip. In this work, we use a flip-chip process to bond a chip with superconducting flux qubits to another chip containing structures for qubit readout and control. We demonstrate that high qubit coherence (T1, T2,echo > 20 μs) is maintained in a flip-chip geometry in the presence of galvanic, capacitive, and inductive coupling between the chips.Addressing qubits in a large-scale quantum processorSuperconducting qubits are a leading technology for realizing a quantum computer. To date, experiments have demonstrated control of up to ten qubits using interconnects that laterally address the qubits from the edge of a chip. Extending to larger numbers, however, will require utilizing the third dimension to avoid interconnect crowding and enable control and readout of all qubits in a two-dimensional array. Danna Rosenberg and a team led by William D. Oliver at MIT Lincoln Laboratory and MIT campus have developed a 3D design for efficiently addressing large numbers of qubits, comprising a stack of three bonded chips, each of which performs a different function. The team performed a proof-of-principle experiment using two bonded chips, demonstrating off-chip control and read out of a qubit without significantly impacting the quality of the qubit performance. This demonstration is an important step towards the 3D integration required to build larger-scale devices for quantum information processing.

Monolithic 3.3 V CCD/SOI-CMOS imager technology

We have developed a merged CCD/SOI-CMOS technology that enables the fabrication of monolithic, low-power imaging systems on a chip. The CCDs, fabricated in the bulk handle wafer, have charge-transfer inefficiencies of about 1/spl times/10/sup -5/ and well capacities of more than 100,000 electrons with 3.3-V clocks and 8/spl times/8-/spl mu/m pixels. Fully depleted 0.35-/spl mu/m SOI-CMOS ring oscillators have stage delay of 48 ps at 3.3 V. We demonstrate for the first time an integrated image sensor with charge-domain A/D conversion and on-chip clocking.