J.M. Knecht

A wafer-scale 3-D circuit integration technology

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

Megapixel CMOS image sensor fabricated in three-dimensional integrated circuit technology

A 1024/spl times/1024 integrated image sensor with 8 /spl mu/m pixels, is developed with 3D fabrication in 150 mm wafer technology. Each pixel contains a 2 /spl mu/m/spl times/2 /spl mu/m/spl times/7.5 /spl mu/m 3D via to connect a deep depletion, 100% fill-factor photodiode layer to a fully depleted SOI CMOS readout circuit layer. Pixel operability exceeds 99.9%, and the detector has a dark current of <3 nA/cm/sup 2/ and pixel responsivity of /spl sim/9 /spl mu/V/e at room temperature.

MEMS microswitches for reconfigurable microwave circuitry

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 /spl Omega/, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S/sub 22/ less than -0.7 dB across the 5-40 GHz band.

High-precision film thickness determination using a laser-based ultrasonic technique

A noncontact and nondestructive laser-based acoustic technique called impulsive stimulated thermal scattering (ISTS) is used to measure thicknesses of metal films including Cu, Ta, W, Al, Ti, and others in single-layer and multilayer assemblies on silicon substrates. Other opaque film materials and substrates have also been examined. Thicknesses are determined with a repeatability of a few angstroms with data acquisition times of about 1 s. ISTS and conventional measurements (scanning electron microscopy, profilometry, and four-point electrical sheet resistance) are made on the same samples and the results are found to compare favorably.

Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers

A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization

High-performance fully-depleted SOI RF CMOS

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.

Generation and Propagation of Single Event Transients in 0.18-

Single event transients were characterized experimentally in fast logic circuits fabricated in 0.18-mum FDSOI CMOS process using laser-probing techniques. We show that the transient pulse widens as it propagates; the widening is largely eliminated by the body contact. Good agreement is observed between pulsed-laser and heavy ion testing.

\mu{\rm m}

A cutoff frequency, f/sub T/, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 /spl mu/m. The p-MOSFET with 0.22-/spl mu/m gate length has an f/sub T/ of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed.

Fully Depleted SOI

This paper describes the development of the 3D via etch process.The oxide via etch was developed in a Trikon Technologies low pressure, high density, helicon-based cluster tool. A response surface design-of-experiments (DOE) was performed varying etch pressure and wafer bias to examine their effect on etch profile and etch rates. An anisotropic etch is essential for high packing density. There was an excellent fit between the data and the model. Low pressure and high bias were required to give vertical profiles. Higher etch pressure caused excessive polymer deposition resulting in etch stop. Low wafer bias could not remove the deposited polymer fast enough, also resulting in etch stop.

High-frequency characterization of sub-0.25-/spl mu/m fully depleted silicon-on-insulator MOSFETs

The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.